Eliyan, a start-up that last year raised $40 million from Intel, Micron, and more to fund a better way of linking multi-die chiplet components, reached a manufacturing milestone recently, and just in time to show off that technology’s strengths amid new demand posed by generative AI.
The Santa Clara, California, company announced it achieved the “first silicon” manufacturing milestone, implemented in a standard 5nm process from semiconductor manufacturer TSMC Corporation. The achievement validates the company’s NuLink PHY technology, a chiplet interconnection approach that both improves on and is compatible with UCIe.
The new chip operates at 40Gbps/bump, delivering over 2.2 Tbps/mm of beachfront bandwidth at 130um pitch on standard organic packaging, and meets the company’s aggressive power and area targets, Eliyan said, adding that NuLink PHYalso is bump-limited and, leveraging interference cancellation techniques, can deliver up to 3 Tbps/mm once implemented on available standard packaging technologies at finer bump pitches.
In an email to Fierce Electronics, Eliyan officials explained what comes next, now that it has successfully reached the first silicon stage: “Now that the technology is silicon tested and characterized, we will focus on the next steps in commercialization. We are in deep discussions with multiple customers and partners with strong interest in using Eliyan’s IP and chiplet products,” they said.
Early results from those discussions are promising, as company officials offered the example of one potential customer that was able to achieve “more than 8 Tbps of bandwidth on a single edge of a silicon chiplet.”
In addition to working with TSMC, Eliyan also is talking to other potential manufacturing partners, with the company saying its technology is “easily portable” to other semiconductor processes.
Standards efforts also are in play. “As the use of chiplets and multi-die architectures continue to evolve, Eliyan is also working diligently through standards efforts like JEDEC and the UCIe Consortium to help further accelerate the growth of chiplet based products,” the officials stated.
All of that progress comes as generative AI has become a top influencer for the next era of computing and how semiconductors will need to be designed in response.
“Generative AI is a major market driver in its early stages of accelerated growth, and we are seeing much interest from hyperscalers, AI processor companies, data centers, memory suppliers, etc. as they try to meet the demand, as well as performance, power, and costs requirements,” Eliyan officials said. “This growth is however limited by capacity constraints at various ecosystem participants (wafer, testers, substrate, packaging, and assembly) as well as access and ability to manage the required power. Our approach provides a way to address these issues.”
In a statement provided by Eliyan, John Lorenz, Senior Analyst, Computing and Software Solutions at Yole Intelligence, supported that claim.
“The economics of adopting a chiplet approach for IC design are tightly linked with the cost and maturity of the interconnect and packaging solution, as we demonstrated in our analysis,” he said. “Eliyan’s chiplet interconnect technology will make multi-die approaches more attractive to chip suppliers whose designs must optimize on power and bandwidth vectors. This is especially the case for those in accelerated server computing applications, a market mainly served by datacenter GPU hardware, and which we see sustaining a 22% unit growth CAGR through 2028.”
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