Eliyan, a Santa Clara, California-based start-up, has an idea for improving interconnection between chiplets, the new architectures using modular building blocks to scale up processing power, and that idea has just earned the company $40 million is Series A funding.
The funding round was by Tracker Capital Management, but by far the two most intriguing participants in the round were Intel Capital and Micron Ventures, the investment arms of the major semiconductor players Intel and Micron Technology. L.P. Celesta Capital also participated.
In addition to the funding, Eliyan also announced the successful tapeout of its technology on an industry standard 5-nm process from TSMC. The new funding and success tapeout are enabling Eliyan to fast-track design, testing, and implementation of its technology, for which its will have its first silicon in the first quarter of next year, the company said.
That technology, called NuLink, is being positioned as a multi-die packaging standard for connecting multiple chiplet components. That will be key as more semiconductor firms want to create complex chiplet architectures without sacrificing bandwidth, power efficiency, and latency in targeted applications like data center processing, cloud computing, AI and graphics.
Though some chiplet interconnection solutions, like Intel’s own Universal Chiplet Interconnect Express (UCIe) standard, address these issues, Eliyan is looking to improve upon what they can do. The company in a statement described NuLink as “backward compatible” to UCIe. Eliyan also described NuLink as a “superset” of UCIe and the Bunch of Wires scheme invented by Eliyan CEO and co-founder Ramin Farjadrad, and which also has been adopted by the Open Compute Project (OCP).
The successful tapeout confirms Eliyan’s ability to achieve twice the bandwidth at less than half the power consumption of current interconnect methods, and does so using a standard SIP manufacturing and packaging process, the company claimed.
In addition to inventing NuLink, Farjadrad in the past has contributed to creating connectivity technologies such as PAM4 SerDes, Multi-Gbps Enterprise Ethernet, and Multi-Gbps Automotive Ethernet that were eventually adopted as IEEE Standards, according to Eliyan
“Technology scaling using conventional system on chip (SoC) architectures is hitting the wall, requiring a new approach in how we integrate and manufacture silicon,” Farjadrad said. “Our extensive background in developing bleeding-edge technologies in this space led us to focus on a key challenge: interconnect improvements for system-in-package and chip-to-memory architectures as the path to deliver performance scaling. Our approach supports and is compliant with the overall industry move toward chiplet-optimized interconnect protocols, including the UCIe standard as well as High Bandwidth Memory (HBM) protocols. This financial investment by industry leaders and the successful implementation of our design in 5nm validates our strategy and prepares us for broader commercialization efforts.”