How to fast track ubiquitious IoT with low power designs

In the era of smart watches, semi-autonomous vehicles, fitness trackers, and more, it’s impossible to deny that the internet of things (IoT) has taken over virtually every facet of our lives. The demand for instant everything has reached an all-time high with no signs of slowing down.

At the core of these IoT devices are pervasive cloud computing and machine learning processes that are enabled by connectivity with the unique ability to siphon large amounts of information over the internet or to the datacenter. While IoT devices have been a part of the technological landscape for a while now, it’s their connection to the cloud that has uncovered exponential possibilities.

The core issue chip designers are having to contend with, however, is that consumers now expect a constant innovation cycle of cost reductions with the desire for their IoT devices to be increasingly compact and instantaneously responsive. As a result of these demands, chip designers have had to make difficult decisions compromising important features such as connectivity, personalization, and sensor processing, all for adequate battery life at specific cost targets.

Design teams today are investigating every avenue to develop devices with architectures that can support multiple wireless connectivity standards and facilitate optimal power efficiency yet provide additional value, many times adding some AI decision making capabilities.  This has spurred the adoption of additional power reduction technologies that certain industries have utilized for decades but were previously cost prohibitive of the vast majority of SoCs.

Globally, companies are developing additional features and functionality for the portable gadgets we use on an everyday basis. A key differentiator for the success of these products is improved battery life through reduced power consumption of complex processing tasks.

Inside IoT edge devices, the underlying silicon performs three main functions: sensing, processing, and communication. What has caused the industry’s rekindled interest in low-power designs is the increasing market demand for IoT devices to have high performance, long battery life, and mobility.

Fundamentally, the objective of low-power design is to reduce both dynamic and static components of power consumption as much as possible. The value of each of these power components is directly related to factors like frequency, peak current, voltage, and more. To obtain optimal performance while consuming the least amount of power, compromises for each of these factors are tested through a variety of low-power techniques and approaches to meet growing market demands.

When developing low-power designs, there are multiple methods to choose from:

·       Multi-voltage domains: Through this process, the operational components of a chip are allocated into various voltage domain blocks contingent on performance features. Rather than the whole area being classified as high-performance, the fundamental design contributes to which area of the chip needs a higher voltage to function properly.

·       Power gating: Based on their power domain, functions within an IC are divided into blocks, much like the multi-voltage approach. This procedure essentially turns off the power entirely for a block, resulting in both static and dynamic power savings.

·       Register retention: In this technique, either a subset of the flops or all the flops in the block have their previous values saved when the block is turned off; when turned on, the values are recovered. By shortening the time and steps necessary to restore the block’s original state, this improves the overall ramp-up time as well as saves power. This method is often used in tandem with the power gating technique.

·       Clock gating: By decreasing the overall switching activity and the demand for several multiplexers, clock gating reduces the dynamic power used and saves a substantial amount of area.

In addition to the above low-power design methods, compressed AI algorithms will need to be managed effectively that may provide less flexibility but much lower power.  This pivot in ideology has altered the IoT design world and thoroughly changed the conversation about power as hardware and software co-design become more prevalent.

To tackle the world’s desire for instant connectivity, increased mobility, and the increasing deployment of artificial intelligence, companies will have to invest in upgraded SoC design techniques, design optimization, and customization tools that model the system with specific IP hardware and software.

The IoT design roadmap will be paved with enhanced operational efficiencies that may delay a next generation cost reduction but will clearly add significant value to users.  

Ron Lowman is Strategic Marketing Manager for Synopsys Solutions Group.