SAN JOSE, CA -- Xilinx, Inc. announces that it will highlight multiple next generation Ethernet, SDN and data center acceleration technologies in presentations and demonstrations at Ethernet Technology Summit 2015 -- ETS Booth #100, April 15 - 16, at the Santa Clara Convention Center, Santa Clara, CA.
Xilinx Conference Participation
Wednesday, April 15
8:30 am – 9:40 am, Forum 1A
Why 25GbE Is the Best Choice for Data Centers by Gilles Garcia, Director of Wired Communications at Xilinx
•This presentation discusses how 25G Ethernet IP for FPGAs addresses throughput challenges in data centers, offers new opportunities to upgrade 10G connectivity, helps reduce data center TCO, and delivers a large performance increase for servers and top of rack switches.
9:50 am – 10:50 am, Forum 1A
400GbE: Current Status and Issues by Mark Gustlin, Principal System Architect at Xilinx
•An update will describe 400GbE current status and the major issues under consideration, including current thinking about the architecture. The issue of defining logic layers to support the requirements of carrying 400 Gb/s of data across up to 16 physical lines with complex encoding needs will be discussed.
3:20 pm – 4:25 pm, Session B
Maximizing Application Acceleration with FPGAs by Shreyas Shah, Data Center Architect at Xilinx
•This presentation provides an in-depth understanding of FPGA applicability in application acceleration markets and the significant role FPGA plays in data centers.
4:50 pm – 5:40 pm, Forum 1C
FlexEthernet: A Single Protocol for All Ethernet Interfaces by Mark Gustlin, Principal System Architect at Xilinx
•Learn how FlexEthernet is being defined and how a FlexEthernet interface operates. Details of the proposed protocol and how it coexists with existing Ethernet will be discussed.
Thursday, April 16
8:30 am – 9:40 am, Forum 2A
Implementing SDN in FPGAs over All Gigabit-Level Ethernet Standards by Gordon Brebner, Distinguished Engineer at Xilinx
•This talk explains how the Xilinx® SDNet™ design environment allows the specification of packet processing data planes for software defined networking, and how it can provide the automatic compilation of the same high-level specification to hardware implementations that operate in the 1G to 400G range. It will also discuss how FPGA technology can be deployed without deep hardware expertise and without requiring different hardware for differing Ethernet speeds and differing packet processing functions.
9:50 am – 10:50 am, Forum 2A
Ethernet in Cloud Radio Access Network (RAN) Fronthauling by Harpinder Matharu, Senior Product Manager at Xilinx
•This presentation discusses how use of Ethernet in the Cloud RAN fronthaul, while identifying associated challenges, could act as a catalyst to the adoption of SDN/NFV technologies in the wireless infrastructure.
9:50 am – 10:50 am, Session A
400GbE Core Routing Implementation by Paul Mooney, Senior Product Marketing Manager at Spirent, Wael Diab, Senior Director at Huawei, and Gilles Garcia, Director of Wired Communications at Xilinx.
•In this session Huawei, Xilinx and Spirent will discuss their collaboration on an operational 400GbE link using the Huawei N5000E core routing platform, Xilinx® Virtex®-7 FPGAs and the Spirent TestCenter 400GbE test module.
Xilinx Demonstrations – Booth #100
•Single Chip 400GE Solution Featuring the Virtex UltraScale Device
This end-to-end solution demonstration showcases the industry's first single-chip 400GbE solution featuring the Xilinx® Virtex® UltraScale™ VU095 device connected to four sets of Sumitomo Electric CFP4 LR4 modules, connected to the Spirent Communications 400GE test solution with four sets of Oclaro CFP2 LR4 modules.
•Low Latency 4x25G Ethernet MAC Solution
This demonstration utilizes the Virtex UltraScale VCU107 board with the Xilinx low latency 25G Ethernet MAC IP supporting the 25G Ethernet Consortium specification.
For more information, visit http://www.xilinx.com