IDT Announces Wireless 5G Technology Solutions for Xilinx Devices

SAN JOSE, CA --- Integrated Device Technology, Inc. announces RapidIO® Gen3 interoperability with Xilinx UltraScale™ FPGAs, enabling a key technology for global rollout of 5G and other advanced network systems. IDT RapidIO RXS switches, coupled with Xilinx UltraScale FPGAs, deliver the essential combination of ultra-low 100ns latency interconnect and programmable computing with application-specific accelerators needed for 4G advanced and 5G programs.

IDT has also developed a wireless data compression solution on Xilinx Zynq®-7000 All Programmable SoCs, which allows more data to fit into a network fiber or link. This solution is targeted for remote RapidIO units, repeaters, and base stations in the front haul of networks to increase front haul capacity with compression ratios ranging from 2:1 to 3:1. IDT has also developed high-performance timing solutions on Xilinx devices, including IEEE 1588 high-performance time synchronization products to meet time alignment error requirements between 5G RRUs in Cloud Radio Access Networks (C-RAN).

Beyond 5G infrastructure challenges, IDT and Xilinx technologies together solve problems in high-performance computing, hyperscale cloud data centers, mobile edge computing and mission-critical embedded systems.

“With this announcement IDT and Xilinx bring innovation that is essential to the deployment of 5G networks,” said Jag Bolaria, principal analyst at the Linley Group, “Given the high cost of developing these technologies internally, system OEMs benefit from the solutions resulting from this industry collaboration, which builds upon multiple generations of R&D and proven deployments by the two companies.”

The IDT technology is available now. IDT compression IP running at 3:1 ratios in a Xilinx Zynq XC7Z045 FPGA was demonstrated by NAT Europe and Fraunhofer at this year’s Mobile World Congress. IDT and Xilinx recently completed interoperability testing between IDT’s RXS family of RapidIO switches with Xilinx FPGAs at 10.3125 Gbaud per lane. These FPGAs also support transceivers up to 32 Gbaud, providing a path to scale to higher bandwidth connectivity. For more information, visit http://www.IDT.com

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