Xilinx, Inc. reports an achievement in PCI Express Gen4 capability. Together with IBM, the two companies are first to double interconnect performance between an accelerator and CPU through the use of PCI Express Gen4 compared to the existing widely-deployed PCI Express Gen3 standard. Gen4 doubles the bandwidth between CPUs and accelerators to 16 Gbps per lane, thereby accelerating performance in demanding data center applications such as artificial intelligence and data analytics.
IBM and Xilinx have achieved Gen4 interoperability between Xilinx 16nm UltraScale+ devices and IBM POWER9 processors, demonstrating the first-ever PCIe Gen4 capability in a programmable device. For more information, visit http://www.xilinx.com