Xilinx & IBM Double PCIe Interconnect Performance

Xilinx, Inc. reports an achievement in PCI Express Gen4 capability. Together with IBM, the two companies are first to double interconnect performance between an accelerator and CPU through the use of PCI Express Gen4 compared to the existing widely-deployed PCI Express Gen3 standard. Gen4 doubles the bandwidth between CPUs and accelerators to 16 Gbps per lane, thereby accelerating performance in demanding data center applications such as artificial intelligence and data analytics.

 

IBM and Xilinx have achieved Gen4 interoperability between Xilinx 16nm UltraScale+ devices and IBM POWER9 processors, demonstrating the first-ever PCIe Gen4 capability in a programmable device. For more information, visit http://www.xilinx.com

Sponsored by Digi-Key

Analog Devices ADIS16500/05/07 Precision Miniature MEMS IMU Available Now from Digi-Key

The Analog Devices’ ADI ADIS16500/05/07 precision miniature MEMS IMU includes a triaxial gyroscope and a triaxial accelerometer. Each inertial sensor in the MEMS IMU combines with signal conditioning that optimizes dynamic performance.

Suggested Articles

Research shows biggest growth expected in Latin America and Asia, as holographic telepresence emerges

Semiconductor Industry Association makes pitch for tax incentives and grants to chipmakers to compete with other countries as backed by lawmakers

The Semiconductor Industry Association sees significant uncertainty for chip sales in coming months, although May numbers were up by 6% globally.