Faraday Technology Corporation has enhanceed its memory compiler IP offerings on both UMC 40eHV and 40LP processes. Based on UMC's 40nm bit cell and Faraday's design optimization on the peripheral circuit, the recently-launched compilers are able to generate memory instances based on the world's smallest footprint. Especially, the 40eHV SRAM compiler targets at the application of mobile display driver IC for cost competitiveness.
Faraday provided the first SRAM compiler IP once UMC launched 0.213um2 bit cell on 40eHV and 40LP, which shrinks the area by 15%~30% in various instance sizes and configurations compared with the previous smallest bit cell of 0.242um2. Moreover, with Faraday's optimized design architecture, both the area and power consumption can be further decreased without any performance scarification. In some benchmark, Faraday helps reduce the area by 20% comparing with other handcrafted memory instances with the same 0.213um2 bit cell. The achievement is critical to SRAM size-dominated applications such as Full HD and WQHD display driver IC.