Spoiler Alert: RISC-V involves zero new technology. Yet, it has garnered serious international interest over the past 10+ years, since it was conceived by developers at the University of California Berkley in 2010. RISC-V (“risk-five”) is an instruction set architecture (ISA) rooted in reduced instruction set computer (RISC) principles. RISC-V is unique, even revolutionary, because it is a common, free, open-source ISA to which software can be ported, hardware can be developed, and processors can be built to support it.

Since 1981, previous generations of RISC architecture (I-IV) have been developed at the University of California, Berkeley. Some of the most common yet proprietary ISAs are the x86, ARMv8 and AMD64.

Whereas the most commonly used ISAs (until now) are proprietary and require a license and fees for their use, RISC-V has been made available under an open-source license. To further bolster the open-source ISA, the RISC-V Foundation was convened in 2015 to form a “collaborative community of software and hardware innovators based on the RISC-V ISA” and manage its development.

In 2015, the RISC-V Foundation was created in partnership with 29 member companies when the original developers of RISC-V transferred their rights to the foundation. In 2020, the foundation was renamed RISC-V International upon its incorporation in Switzerland. The organization has grown to 2,000+ members from more than 70 countries over the span of just a few years. Members of RISC-V International include founding partners Google, Qualcomm and Western Digital, to name a few, as well as Arduino, Hitachi and Samsung.

To understand why RISC-V is so approachable—even beyond its most alluring, open-source feature—we can take a closer look at its other important attributes.

RISC-V Characteristics

  • Is a proven ISA and follows established RISC design principles
  • Has single-cycle instructions
  • Uses a load-store architecture
  • Features a simple, stable, software-centric design (small, fixed base with modular fixed-standard extensions)
  • Is modular, layered and extensible, allowing for software and hardware freedom on architecture
  • Flexible and scalable (i.e., suitable for microcontrollers to personal computers to supercomputers)
  • Has 32- and 64-bit variants and extensions to support floating point instructions
  • Is supported by various language compilers (e.g., GNU Compiler Collection and Linux operating system)
  • Offers a range of hardware support from microcontrollers to systems on module, systems on chip and field programmable gate arrays
  • Accelerates the design-to-market timeline through collaboration and open source IP reuse


RISC-V Applications

As developers and manufacturers of all types and sizes continue to embrace RISC-V, software, hardware and processors built for and around this open-source ISA will proliferate. RISC-V will become ubiquitous and is predicted to pave “the way for the next 50 years of computing design and innovation.”

Various applications for RISC-V include:

  • Artificial intelligence
  • Augmented reality
  • Automotive
  • Cloud servers
  • Computer devices and controllers
  • General purpose processors
  • Internet of Things
  • Machine learning
  • Network edge
  • Virtual reality

The proven, open-source nature of RISC-V is crucial because it allows smaller developers and manufacturers to design and build hardware without the cost of licensing proprietary ISAs and paying royalties. As a result, companies of all sizes can innovate and create, putting the best products on the market for the advancement of the industry and benefit of the consumer.

risc-v board illo

Further notes + research

Pronounced "risk-five," RISC-V is an ISA based on reduced instruction set computer (RISC) principles.

An Instruction Set Architecture (ISA) is part of the abstract model of a computer that defines how the CPU is controlled by the software. The ISA acts as an interface between the hardware and the software, specifying both what the processor is capable of doing as well as how it gets done.

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