TEL AVIV, Israel -- Vtool, a pioneer of advanced EDA solutions for accelerating verification environment creation, debug and management will demonstrate its disruptive functional verification platform at DVCon conference 11-12 November 2015 in Munich, Germany.
Vtool Ltd. develops and markets Vtool, a functional verification platform that significantly improves the ability of engineering teams to create, execute, debug and document UVM verification environments in an efficient and precise way.
"We are thrilled to exhibit Vtool at DVCon Europe. We empower innovation, helping engineers to increase productivity and enabling semiconductor companies to reduce time-to-market," said Hagai Arbel, CEO, Vtool
Vtool is entirely focused on making functional verification environments easy to create, maintain and debug. Vtool automatically generates and synchronizes the UVM framework, leaving the engineers to focus on the creative verification core tasks rather then the housekeeping of syntax, integration and reuse issues.
Vtool goes way beyond a simple Integrated Development Environment (IDE) solution by providing a visual representation of the verification environment. The Vtool visual UVM representation optimizes the creative process, making the verification environment easy to understand and develop. Its debugging solution allows issues to be quickly identified and highlighted from the mass of simulation log data, streamlining the entire debug process. Vtool continuously synchronizes with existing UVM code, fostering testbench reuse and team cooperation. Vtool works with all major simulation tools and the entire SystemVerilog UVM standard.
For more details, visit http://www.thevtool.com