Keyssa claims its Virtual Pipe I/O (VPIO) architecture enables I/O to scale with processor/memory performance and allows product designers to develop new classes of consumer and industrial products. Reflecting that statement, the company’s next-generation solid-state connector, the KSS104M is now in mass production.
Keyssa is making available its VPIO architecture to system architects, SoCs, processors, and system partners. VPIO has been designed to take in low- and high-speed signals from any protocol and aggregate them into one virtual channel over a "virtual pipe," transmit the aggregated signals to their destination and disaggregate on the other side. The separate pads, pins, and PHYs required for specific protocols can now be combined into one pipe and transmitted over one or more standard SerDes or Keyssa RF link.
Ajay Bhatt, former chief I/O architect for Intel and co-architect of VPIO expounds, “Every chip and system designer struggles with an immutable fact: there is no Moore's Law for pins. And with the myriad of low- and high-speed legacy protocols that exist in every processor and every system, I/O cannot scale with processor and memory performance. VPIO provides a viable and effective way for I/O to scale by replacing pads with gates, providing both I/O flexibility and scalability.”
The KSS104M embarks as the only solid-state contactless connector on the market. It is described as a tiny, low-cost, low-power, solid-state electromagnetic connector that enables large amounts of data to be securely transferred between devices at very high speeds. Reportedly, it can be easily integrated into customers' end products without requiring any changes to software or firmware, by supporting industry standard high-speed data and video protocols. For more information, visit VPIO and Keyssa.