UMC Broadens its 55nm eFlash Platform with Faraday's Silicon-proven IP

Faraday's IPs with HVT Core Devices Reduce Power by Up to 65% to Target Power-sensitive Market Applications

HSINCHU, Taiwan -- Faraday Technology Corporation and United Microelectronics Corporation announce the availability of a complete set of low power consumption fundamental IPs developed for UMC's 55nm Low Power (LP) embedded Flash process. These IPs are designed to simultaneously meet both low-power and high-density requirements to satisfy the demands of a broad range of applications including IoT (Internet of Things) and wearable products.

Low-power is prioritized for always-on devices in order to extend battery life. To fulfill the requirement, Faraday's memory compilers greatly reduce power consumption in the standby mode by up to 70% through optimization of the low leakage memory periphery. The robust I/O cells are available for both digital and analog interfaces, with a high voltage I/O cell option available that is especially compatible with a 5.0V interface. These IO cells are designed by using HVT core device to reduce leakage power. Furthermore, the IP suite also includes a new low-power USB 2.0 OTG PHY with HVT core device, which significantly reduces power consumption in the idle mode by up to 65% over traditional USB 2.0 OTG PHY.

"Faraday has been cooperating closely with UMC to build robust platform solutions for power-sensitive applications spanning from 0.18um to 0.11um, and now on 55nm eFlash," said Jensen Yen, associate vice president of marketing and spokesperson at Faraday Technology. "Our IP expertise and high familiarity with UMC processes led to these newly-launched IPs with UMC's HVT core devices that significantly reduce power consumption, greatly catering to the growing IoT market. With this important milestone and our continuous collaboration with UMC, we are confident that our mutual customers will soon be able to seize new business opportunities in the IoT market."

"UMC continues to broaden our strong IP portfolio to bring more low-power benefits to IoT chip designers," said Shih Chin Lin, senior director of IP Development & Design Support Division. "Our 55nmLP SST embedded flash technology is a widely adopted, mass production process that is supported by strong IP and design resources. We are happy to add Faraday's IP as part of our 55nm platform resources to help customers broaden their opportunities in power-sensitive applications. We look forward to working with them to deliver future IP solutions in the future."

Faraday's complete IP set on 55nmLP SST embedded Flash process includes the standard cell libraries, memory compilers, diffusion programmable ROM, Via ROM, I/O cells, and low power USB 2.0 OTG PHY. The 3-series cell libraries, 7-track miniLib™, 8-track generic libraries, and 12-track UHS-Lib™ are all equipped with the low-power management of PSK cells and multi-Vt options.

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