MOUNTAIN VIEW, CA -- Synopsys, Inc. announces availability of the industry's first verification IP (VIP) and UVM source code test suite for Ethernet 200G. As the requirements for increased bandwidth to support video-on-demand, social networking, and cloud services continue to grow, Synopsys VC VIP for Ethernet 200G enables system-on-chip (SoC) teams to design next-generation networking products with better ease of use and higher verification productivity, resulting in accelerated verification closure.
Synopsys VC VIP for 200G supports 4x50G or 8x25G line interface options with RS-FEC. Synopsys VIP uses a native SystemVerilog/Universal Verification Methodology (UVM) architecture and features built-in comprehensive coverage, verification planning, extensive protocol checks and protocol-aware debug. It features extensive and customizable frame generation and error injection capabilities, with additional source code UNH-IOL test suites also available. Synopsys VIP is also natively integrated with the Verdi® Protocol Analyzer debug solution for the highest debug productivity.
Synopsys VC VIP for Ethernet 200G and source code test suites are both in limited customer availability today. Learn more at http://www.synopsys.com