MOUNTAIN VIEW, CA -- Synopsys, Inc. announces the availability of the industry's first Verification IP (VIP) and source code test suite for DisplayPort 1.4 with DSC 1.2 and for eDP 1.4a/b. With the increase in consumer demand for enhanced display resolution quality, Synopsys VC VIP for DisplayPort enables system-on-chip (SoC) teams to design these next-generation displays with ease of use and integration, resulting in accelerated verification closure.
Synopsys VC VIP for DisplayPort 1.4 delivers advanced support for the highest display resolutions. It also features display stream compression (DSC) for visually lossless low-latency algorithms, increased resolution and color depths, and reduced power consumption. Synopsys VIP uses a Native SystemVerilog/UVM-based architecture to design next-generation display chips with optimum performance. Synopsys VIP is natively integrated with the Verdi® Protocol Analyzer debug solution and features advanced debug ports. The VIP also features error injection capabilities, built-in-protocol checks, coverage and verification plans.
Learn more at http://www.synopsys.com