Every online purchase we make, every interconnected device we access from smart refrigerators to emerging software-defined cars, all add to data traffic. These interconnected devices, the data that is their lifeblood, and the AI and ML brains driving them, require big, complex SoCs and present significant integration challenges.
As a result, plug-and-play is not what it used to be and must be customized by designers for specific use cases. But what if, instead of coming with standalone functions leaving customization to the designer, IP followed the ASIC model? In other words, what if EDA companies and other IP providers offered IP with complete application-based solutions?
Most applications today need customizing. In the data center, for example, the space between ICs can be 12 to 14 inches. When designing for PCI Express® (PCIe®), high performance is a priority over low power to bridge those gaps. Alternatively, for cell phones with a limited battery life, low power is the priority over higher performance. While IP may give you standard functions, the devil is not only in managing the power-performance-area (PPA) and-latency details, but also the integrations. There are many design-by-design inconsistencies depending on your application: clock speeds, I/Os (quantity and type), lane count, and more.
Similar to the ASIC model, where chips are customized for specific use cases, software IP can come with a comprehensive solution for specific applications. The good news is that IP providers are stepping up to create these complete solutions for a wide range of application scenarios, whether your needs are feature differentiation, PPA and latency differentiation or other customizations, including pitches, metal stacks, or something else.
When evaluating these companies to meet your IP needs, ensure that they have a broad portfolio. This translates into a consistent and more streamlined user experience and broader support. Check that they also have the strong industry relationships in place so they can characterize and run your test chips for you, and that they have a spread of generations and architectures to accommodate a wide variety of PPA and latency scenarios.
In addition to providing the IP block, use an EDA or IP vendor who can provide the comprehensive subsystem solution, pre-verified with the appropriate collateral, support, and guidelines to back it all up. These can include feasibility studies, packages substrate guidelines, signal and power integrity models, crosstalk analysis, and more. Ensure your vendor has a solid history and relationships with the ecosystem of partners including system providers, test equipment providers, and foundries, and that they have a deep understanding of process geometries and where these geometries are headed.
Providing IP that follows the ASIC model is no small undertaking for IP providers. The due diligence required to do it right is expansive, encompassing tasks such as recreating large SoC designs and putting them through their paces, including full integration exercises, taking IP from die to package substrate and to the board. The whole process should verify that there are minimal layers for high-speed package escapes. Also, this due diligence should also include SoCs with hundreds of lanes together, and a deep understanding of the cross talk and the IR drops, and much more. As you vet your IP provider for their ability to provide comprehensive application-specific IP solutions, ask them about the due diligence behind these complete solutions.
Developers are no longer alone to do the difficult IP integration work, thanks to the shift that some IP providers have taken toward a more application-specific model. Choosing the right vendors will help you by giving you integration guidance for your application. While comprehensive application-specific IP solutions don’t cover every corner case, these vendors can use the experience of others to build their libraries of application-specific solutions for you to leverage. The application-specific IP model has arrived. It will spare you the pain of seemingly endless iterations and ease your design path, so that you can utilize fewer resources, reduce your risks, get to market faster and improve your bottom line.
Manmeet Walia is Product Marketing Director at Synopsys Solutions Group. He brings more than 20 years of experience in product marketing, product management, and system engineering covering ASSP, ASIC, and IP products for a broad range of applications. Manmeet holds an M.S. in electrical engineering from the University of Toledo and an MBA from San Diego State University.