JTAG Visualizer Gets Faster

JTAG Technologies’ latest version of its Visualizer graphical viewing tool for board (PCB) layouts and schematics allows users to assess fault coverage data and pin-point production test faults significantly faster. With its wide range of CAD (EDA) tool import filters, users can import schematic data direct from Mentor (Pads, DxDesigner, Capture) Cadence, Altium and Zuken tools as well as board layout information in ODB++ and a dozen other vendor specific formats.

 

Introduced in this version of Visualizer, the new Maps feature offers a basic test-accessibility view by a simple click of the mouse. The view can easily be fine-tuned by adding just a few key component descriptions to a look up table. What’s more using customizable colors to indicate test coverage levels or access types, a color-coded schematic can be displayed or printed. Once the design has been optimized for boundary-scan test coverage and committed to layout, final application development can begin in the JTAG ProVision developer tool.

Sponsored by Infosys

Infosys positioned as a Leader in Gartner Magic Quadrant for IT Services for Communications Service Providers, Worldwide 2020

The Gartner Magic Quadrant evaluated 12 vendors and Infosys was recognized for its completeness of vision and ability to execute.
Infosys leverages its global partner ecosystem, CSP-dedicated studio, design tools, and 5G Living Labs to boost service delivery. Innovative solutions such as the ‘Infosys Cortex2’ are driving business value for CSPs.

 

Additional New Features

  • Visualize on (Test) Fail -When running a test sequence or during test debug within ProVision it is now possible to view all failing circuit nets on a schematic view, a layout view or both – automatically. This feature is ideal for small-scale production systems where the test operator is also responsible for fault diagnosis and rework.
  • Locate Next – during fault-finding the ‘locate next’ feature allows the user to track the course of a net connection through the layers of a PCB layout or the sheets of a schematic.
  • Multiple Color Themes - users can now define multiple color themes for distinguishing different net classifications e.g. for percentage fault coverage in schematics or fault nets in layouts to aid in debug and repair
  • View through layers - a highlighted fault net, perhaps because of a detected board connection fault, can now be viewed along its entire path and as it changes course through the board layers.
  • Add notes – A note can be added anywhere at a fixed position on the schematic or layout. Ideal for conveying additional information about test processes or passing design details back and forth between users. 

For more enlightenment, visit JTAG Technologies.

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