Imperas and T&VS Partner to Update Software Verification and Validation Methodology for Embedded Systems

Oxford, United Kingdom --- Imperas Software Ltd. and Test and Verification Solutions (T&VS) partner to promote state-of-the-art software verification and validation (SW V&V) methodologies for embedded systems.

Imperas offers virtual platform (software simulation) based tools and solutions for early software development and more comprehensive software testing. In addition to SW V&V, use cases include porting and bring up of hypervisors and operating systems, advanced software analysis such as non-intrusive code coverage, profiling and memory monitoring, and support for advanced methodologies such as Continuous Integration (CI) and fault injection. Imperas offers a wide variety of processor models and systems architectures from a range of IP and chip vendors through Open Virtual Platforms (OVP) models and platforms.

T&VS offers hardware verification methodology experience, and embedded software expertise. T&VS provides specialist test and verification services and products to the worldwide semiconductor and embedded systems industries, delivering advanced solutions in test and verification methodologies and tools.

T&VS will provide services to the embedded systems community to help them adopt virtual platform tools and methodologies for software development, debug and test.

Virtual platform based methodology is complementary to hardware based flows, incorporating techniques such as code coverage and fault injection, which are required by automotive software developers, in compliance with ISO 26262. The Imperas tools are non-intrusive, providing necessary visibility, controllability and repeatability.

For more details, see:
http://www.testandverification.com
http://www.imperas.com