FPGAs Ramp Up For 112G PAM4

At OFC 2018, Xilinx provides a glimpse into the future of networking with the FPGA industry's first demonstration of 112G PAM4 electrical signaling technology for optical networks, as well as announcing the addition of 58G PAM4 transceivers to its 16-nm Virtex UltraScale+ portfolio. Anticipating greater demand for speed and throughput, Xilinx is demonstrating full-duplex 112G PAM4 signaling on a single lane. Industry experts regard 112Gb/s transceiver performance as necessary to address next-generation optical networking and line card densities. Users can expect programmable devices with 112G transceivers in Xilinx's upcoming 7nm portfolio.

 

58G PAM4 FPGAs

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Built on the Virtex UltraScale+ class devices, the latest transceiver architecture enables users to effectively double the bandwidth capabilities of existing systems by combining the flexibility of programmable logic with 58G PAM4 transceivers. These devices can operate over existing 25G backplanes, extending the life and bandwidth of current systems while paving the way for the next generation. For migration, the new devices with 58G transceivers are footprint compatible with existing Virtex UltraScale+ devices in production today. Targeted at cloud computing, 5G networking, core networks (OTN, Ethernet) and network functions virtualization (NFV) applications, this latest transceiver architecture will enable vendors to scale 50G, 100G and 400G ports and terabit interfaces in compact and less complex system designs.

 

The new 58G PAM4 Virtex UltraScale+ devices include integrated PAM4 transceivers, 100GE IP blocks, and all associated FEC required for next-generation interconnect. For more information, visit Xilinx.

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