SAN JOSE, CA --- Cadence Design Systems, Inc. announces its OrCAD® Capture has been enhanced to now include XJTAG® DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays.
XJTAG DFT Assistant is composed of two key elements: XJTAG Chain Checker and XJTAG Access Viewer. XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected and terminated test access ports (TAPs), and reports them to the developer. Otherwise, a single connection error would inhibit the entire scan chain from working. XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage can be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets without any JTAG access on the schematic.
While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from OrCAD Capture to the XJTAG development software, where additional tests can be developed. Hardware can then be tested as soon as it is available.
XJTAG DFT Assistant software is now included with OrCAD Capture 17.2-2016 QIR 2 at no additional cost; users of version 17.2 or higher can download the software today from http://www.xjtag.com/orcad
For more information, visit http://www.orcad.com/xjtag-orcad