Cadence Modus Test Solution Enables Support for Safety-Critical SoC Designs Using ARM MBIST Interface

SAN JOSE, CA -- Cadence Design Systems, Inc. announces that the Cadence Modus Test Solution now supports the ARM Memory Built-In Self Test (MBIST) interface, enabling customers to efficiently create safety-critical system-on-chip (SoC) designs using high-performance ARM processors. To demonstrate the success of the collaboration, Cadence and ARM have completed silicon validation using an ARM Cortex-A73 processor in conjunction with the Modus Test Solution's automatic test pattern generation (ATPG) and diagnostic capabilities.

Through Cadence's support of the ARM MBIST interface, customers can deliver innovative SoC designs to market faster and with better power, performance and area (PPA). For example, the Modus Test Solution provides ARM MBIST interface users with the option for programmable memory built-in self test (PMBIST) to use a single bus to service multiple memories with one MBIST controller. The solution utilizes the ARM MBIST interface to reduce the impact of MBIST on critical timing paths to and from memories in functional operation and for a higher quality at-speed test. Finally, the Modus Test Solution provides a physical-to-logical mapping capability, which reduces the need for manual, error-prone work.

The Cadence Modus Test Solution is a comprehensive next-generation physically aware design-for-test (DFT), ATPG and silicon diagnostics tool. Using the Modus Test Solution, customers can experience up to 3X reduction in test time using its patented physically aware 2D Elastic Compression architecture, without any impact on fault coverage or chip size.

For more information on the Modus Test Solution, visit

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