3D NAND Architecture Rockets I/O Performance

Yangtze Memory Technologies’ Xtacking 3D NAND architecture is said to provide unprecedented NAND I/O performance, higher bit density, and enable faster times to market. With Xtacking, the periphery circuits that handle data I/O and memory-cell operations are processed on a separate wafer using the logic technology node that enables the desired I/O speed and functions. Once the processing of the array wafer is completed, the two wafers are connected electrically through metal vertical interconnect accesses (VIAs) that are formed simultaneously across the whole wafer in one step.

 

In the conventional 3D NAND architecture, the periphery circuits take up 20% to 30% of the die area, lowering NAND bit density. As 3D NAND technology continues to progress to 128 layers and above, the periphery circuits will likely take up more than 50% of the total die area. With Xtacking, the periphery circuits are now above the array chip, enabling much higher NAND bit density than conventional 3D NAND.

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The technology performs fully independent processing of the array and periphery, which offers a modularized, parallel approach to product development and manufacturing, allegedly reducing product development time by at least three months and shortening manufacturing cycle time by 20%. This modular approach also opens possibilities for custom NAND flash solutions. For greater insight, visit the Xtracking page.  

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