Western Digital expands RISC-V role

SiFive launches first open-source, RISC-V-based SoC platform with NVIDIA deep learning accelerator technology
RISC-V will help pave the way for open architectures and Western Digital expects to play a role.

Western Digital Corp. is hedging that RISC-V (an open-source instruction set architecture) will play a key role in the trend toward open architectures to address high-growth applications such as artificial intelligence (AI), machine learning (ML), and Internet of Things (IoT).

To this end, the company has announced a strategic partnership with PlatformIO Labs, OÜ, in collaboration with SiFive, Inc., to extend the openness of the PlatformIO vendor-agnostic embedded development platform.

The agreement includes new tools and creates an end-to-end, open environment for innovation, including development for RISC-V. Western Digital has also unveiled key new enhancements to its open-sourced RISC-V SweRV Core™ and cache-coherent fabric, OmniXtend™.

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RELATED: "Qualcomm invests in Si-Five for RISC-V architecture

PlatformIO enables developers to streamline the design of a wide range of embedded hardware and software technology, supporting numerous leading operating systems (OS) and development platforms, as well as hundreds of boards. The platform’s unified project configuration capabilities leverage built-in package and library managers to automatically install the required library and toolchains, depending on a project build environment.

Developers of RISC-V and other architectures can use now use PlatformIO's previously paid PlatformIO Plus™ features at no cost, including the PIO Plus Unified Debugger and PIO Uniting Testing Engine tools, as well as remote access capabilities.

Engineers can also replicate their project in multiple OS environments, thereby providing greater design flexibility, and eliminate the need to learn complex vendor-specific toolkits. The PlatformIO environment can now provide a fully open-source supportive environment, for end-to-end design of embedded technology, including those by the RISC-V ecosystem.

"By teaming up with PlatformIO, we are bringing the entirety of its multi-architecture embedded design environment, including debug and trace, to the open-source community. With deep libraries and automated support already built-in, this will allow programmers to easily transition among development platforms, including RISC-V," said Martin Fink, chief technology officer, Western Digital, in a statement.

"The expanded openness of PlatformIO, along with our recent enhancements to our SweRV Core and OmniXtend cache-coherent fabric, further lowers the barrier for RISC-V development and expands the potential for innovation that will enable us to realize the benefits of bringing compute power closer to data," he added.

Western Digital has also updated SweRV Core, integrating several improvements that enhance performance and reliability. These include faster divide and fetch functions, the incorporation of I/O timing control, better error correction capabilities, multi-core debug improvements and more. The 32-bit, in-order core was open-sourced to the RISC-V ecosystem by Western Digital earlier this year. The updated core is now available for download.

Western Digital is also making its OmniXtend memory-centric system architecture interoperable with Barefoot Network's end-user P4-programmable Tofino™ Ethernet switch ASIC. OmniXtend, an open approach to providing cache coherent memory-over-an-Ethernet fabric, enables access to and data sharing with a wide variety of components.

Compatibility with the Tofino switch ASIC allows data center architects to implement architectures where the main memory is central to the network. OmniXtend enables cache coherency to be equally shared with GPUs, FPGAs, machine-learning accelerators and CPUs, thus supporting further advancements in data center architectures, CPU micro-architecture, and purpose-built compute acceleration in data-centric devices.


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