Synopsys pushes AI deeper into EDA process for chips

Chips continue to become more powerful, more efficient, and even more customized to the needs of different industries and applications, and that is making the whole process of semiconductor design more complex.

Synopsys co-founder, Chairman and co-CEO Aart de Geus, speaking at this week’s Synopsys User Group event in Santa Clara, California, described the challenge as one of increasing “systemic complexity,” driven by the ongoing increase of transistors on chips, but also the notion that “every different vertical will actually look at creating its own architecture for its own problems, because by narrowing the field, you can go much faster.”

This raises the bar for the electronic design automation (EDA) tools and systems used in the design process. “EDA is essentially getting all the data on a computer,” de Geus said. “If you can capture it, you can model it. If you can model it, you can simulate it. If you can simulate it, you can analyze it. If you can analyze it, you can optimize it, and if you can optimize you can be more productive.”

The answer Synopsys has for improving the EDA process is to push AI into every stage of it, elevating AI from a supporting role in chip design to a starring role as a full-stack EDA solution. At this week’s event, the company announced the EDA suite, which the company said offers capabilities such as:

  • Digital design space optimization to achieve power, performance and area (PPA) targets, and boost productivity (used in 100 production tape-outs by January 2023, according to a previous Synopsys press release).

  • Analog design automation for rapid migration of analog designs across process nodes.

  • Verification coverage closure and regression analysis for faster functional testing closure, higher coverage and predictive bug detection.

  • Automated test generation resulting in fewer, optimized test patterns for silicon defect coverage and faster time to results.

  • Manufacturing solutions to accelerate development of lithography models with high accuracy to achieve the highest yield.

Accelerating chip design processes is clearly on the minds of many on the ecosystem. The announcement comes a week after Synopsys partner Nvidia announced its cuLitho software library for computational lithography, also aimed at speeding design productivity.

Patrick Moorhead, founder, chief analyst and CEO of Moor Insights & Strategy, said in a statement provided by Synopsys that the company is “taking the lead in infusing AI throughout the chip development flow.” He added, “AI is transforming the semiconductor industry, enabling engineers to create more complex chips that humans unaided would be unable to produce.”

Synopsys users weighed in as well. Renesas is already the suite, and Takahiro Ikenobe, IP Development Director, Shared R&D Core IP Division at Renesas, said, “Meeting quality and time-to-market constraints is fast becoming difficult using traditional human-in-the-loop techniques due to the ramp in design complexity. Using AI-driven verification with Synopsys VCS, part of, we’ve achieved up to 10x improvement in reducing functional coverage holes and up to 30% increase in IP verification productivity demonstrating the ability of AI to help us address the challenges of our increasingly complex designs.”

Vivek K. Singh, VP, Advanced Technology Group, Nvidia, added, “AI has the potential to reshape virtually every field, and its benefits for the semiconductor industry are hard to overstate. We’re working alongside leading companies like Synopsys to accelerate and improve production and open new frontiers for the industry.”