Synopsys offers new UCIe IP for the data center chiplet crowd

AI continues to push demand for multi-die chiplet packages in data centers, and with it demand for higher-bandwidth, lower-latency connectivity between semiconductor dies. The Universal Chiplet Interconnect Express (UCIe) specification has progressed over the last two and a half years from 1.0 to 2.0 status to address rapidly changing performance requirements, but Synopsys is thinking bigger.

The company this week announced what it claimed is the industry’s first complete UCIe IP solution–including PHY, controller, and verification IP–operating at up to 40 Gbps per pin. It supports open UCIe environments where there is a need to move more data efficiently across heterogeneous and homogeneous chiplets architectures in AI data center systems.

The announcement likely will be welcomed by Synopsys’ fellow members in the UCIe Consortium, formed by Intel, AMD, Samsung, Google Cloud, and others back in early 2022 with the aim to create a standard approach for enabling  “high-bandwidth, low-latency, power-efficient and cost-effective on-package connectivity between chiplets.” That group, whose efforts began just as the chiplet model was taking off as a way to efficiently boost data center computing power, released its UCIe 2.0 specification within the last month.

In fact, Samsung Electronics already has expressed support for the new UCIe IP package. “Heterogeneous integration with high-bandwidth die-to-die connectivity gives us the opportunity to deliver new memory chiplets with the efficiency needed for data-intensive AI applications,” said Jongwoo Lee, vice president of the System LSI IP Development Team at Samsung Electronics, in a statement. “Leveraging Synopsys' new 40G UCIe IP, we can extend our collaboration to develop industry-leading chiplet solutions for tomorrow’s high-performance data centers."

Synopsys told Fierce Electronics via e-mail that the new 40G UCIe IP “has already been adopted by customers in the HPC, cloud services, and semiconductor design segments. It will be available in late 2024 for multiple foundries and processes.”

Asked how the new IP could inform future UCIe specification updates, the company added, “Synopsys is closely engaged with the UCIe Consortium, and we consistently bring to market advanced IP ahead of industry specifications. Both of these aspects benefit our customers – they can feel confident that our IP will remain UCIe compliant and deliver advanced capabilities.”

Some of those capabilities inherent to the new 40G IP solution include the following:

• Simplified Solution Eases IP Integration: Single reference clock feature simplifies the clocking architecture and optimizes power. For ease of use and integration, the IP speeds up die-to-die link initialization without the need to load the firmware.

• Silicon Health Monitoring Enhances Multi-Die Package Reliability: To ensure reliability at the die, die-to-die, and multi-die package levels, Synopsys 40G UCIe IP offers test and silicon lifecycle management (SLM) features. The monitoring, test, and repair IP and integrated signal integrity monitors enable diagnosis and analysis of the multi-die package from in-design to in-field.

• Successful Ecosystem Interoperability: For on-chip interconnect needs of the latest CPUs and GPUs, Synopsys 40G UCIe IP supports the most popular on-chip interconnect fabrics including AXI, CHI chip-to-chip, streaming, PCI Express, and CXL. For successful interoperability, the IP is compliant with the UCIe 1.1 and 2.0 standards, which Synopsys helps to develop and promote as an active member of the UCIe Consortium.

• Pre-Verified Design Reference Flow: The combination of Synopsys UCIe IP and Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, is used in Synopsys’ pre-verified design reference flow that includes all the required design collateral such as automated routing flow, interposer studies, and signal integrity analysis.

• Broad IP Solutions for Multi-Die Designs: In addition to UCIe IP and high-speed SerDes, Synopsys offers HBM3 and 3DIO IP to enable high-capacity memory and 3D packaging.