Synopsys, TSMC team on 5-nm process for mobile products

Synopsys, TSMC team on 5-nm process for mobile products
Synopsys and TSMC have teamed to qualify Synopsys' Digital and Custom Design Platforms on TSMC's 5-nm process, to meet the needs of high-speed computing and mobile chip products. (Pixabay)

EDA software supplier Synopsys, Inc.  announced it has achieved certification for many features of its Digital and Custom Design Platforms on TSMC's most advanced 5-nm process technology, required for high-performance computing (HPC) and mobile chip designs. In addition to certification of HPC and mobile design flows, Synopsys has also achieved certification for its design tools on TSMC's N5P and N6 process technologies, to enable early customer design work.

"Our close collaboration with Synopsys ensures a well-established design flow to help customers address the requirements on increasing complexities for their HPC and mobile designs and achieve their success of silicon innovations on 5-nanometer processes," said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC, in a statement. "Partnering with our ecosystem, TSMC continues to push the leading edge for enablement of HPC and mobile design solutions on TSMC's most advanced 5-nanometer processes."

Enhancements to multiple design tools in the HPC and mobile design flows enable designers to maximize the advantages of TSMC's 5-nm processes in logic density, performance, and power over previous-generation process nodes. New features in Synopsys Design Compiler Graphical synthesis and IC Compiler II place-and-route were created to handle new 5-nm placement rules for spacing, abutment, and boundary cell insertion.

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Because mobile devices require low power, an increasing variety and usage of low-leakage cells is needed. Therefore, enhancements were also made in IC Compiler II to handle the increased complexity of low-leakage cell placement. As part of the HPC and mobile design flow platform certification, results from Synopsys' StarRC and PrimeTime signoff solutions were compared to implementation results to successfully achieve design flow correlation targets that speed overall time-to-market.

"Rapid innovations in the HPC and mobile markets require SoC teams to explore how best to leverage 5-nanometer process technologies, and it is imperative for us to enable our customers to meet their design and time-to-market requirements," said Michael Sanie, vice president of marketing and strategy of the Design Group at Synopsy, in a statement. "This latest collaboration with TSMC that will better enable HPC and mobile design customers is one part of a continuous endeavor to provide best-in-class solutions for optimized performance, power, and logic density, and help them get to market on time."

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