Siemens on Tuesday launched a new architecture for chip design validation and verification based on a new Siemens accelerator chip and an AMD FPGA to boost chip emulation and prototyping processes used widely by electrical design engineers in the creation of electronics, including AI chips.
The entire new Veloce CS hardware-assisted verification and validation system is expected to be generally available sometime in the summer, but parts or all of it are already being trialed by several customers, including Arm, Siemens told Fierce Electronics. Pricing was not announced.
“Siemens’ Veloce platforms have become an integral part of the Arm development process and we continue to see benefits of the new Veloce Strato CS system for hardware design acceleration and software development," Tran Nguyen, senior director of design services at Arm, said in a statement.
Veloce Strato CS is one-third of the entire Veloce CS announcement, with Strato devoted to hardware for emulation. A second part, Veloce Primo CS hardware, is for enterprise prototyping and the third component, Veloce proFGPA CS hardware, is for software prototyping.
The entire three-part system is designed to accelerate verification and validation cycles by 10 times, while reducing total cost of ownership by up to 5 times, according to Jean-Marie Brunet, vice president and general manager of hardware assisted verification for Siemens Digital Industries, a part of Siemens.
The system can support chip design sizes from 40 million logic gates up to 40 billion-plus gates, with deployments of modular blades that can be inserted into one or multiple cabinets. The new purpose-built Crystal accelerator chip from Siemens supports the emulation in Veloce Strato CS, while Veloce Primo CS is based on AMD’s latest Versal Premium VP 1902 FPGA. Both Strato and Primo run on the same operating system to accelerate ramp up, setup, and debug and workload execution steps.
The third part of the system, Veloce proFPGA CS hardware, is also based on the AMD FPGA and is designed for fast and comprehensive software prototyping. All three parts are qualified to run on AMD EPYC CPU-powered HP DL385g11 servers.
Brunet said the entire system is the industry’s only congruent, high-speed, modular hardware assisted system with three systems. He told Fierce that Cadence and Synopsys are primary competitors in the space.
In addition to faster performance and lower cost of ownership, Siemens has also focused on reducing the cost of electricity needed to power the system, Brunet said. In some modern EDA systems, power consumption can become almost as expensive as the cost of the chip itself, he added. “Sustainability is very important. It’s not a joke-- customers are looking as us very carefully.”
Bringing two chips and three hardware products on the market at the same time gives customers a “complete offering on day one so they can use as many solutions as possible to handle tasks,” he told Fierce. With support for 40 billion gates, “this is the largest emulator in the world,” he added. “It’s a bold move to serve the entire market and we’re clearly going after better position.”
With common software across Strato and Primo, the system runs three to five times faster at half the cost per gate, he added.
Laurie Balch, research director for Pedestal Research, said an advantage of Veloce CS is the potential for chip developers in smaller operations to take advantage of emulation tools. "Emulation is a vital piece of the EDA design flow, but has historically been delivered in a 'big iron' form factor that can present both physical and cost challenges to implement," she told Fierce. "Veloce CS should make emulation accessible to a much wider range of chip devee\lopers..."
Balch said the Siemens announcement is "the first concerted effort to redesign the physical implementation of traditional emullation and prototyping hardware while fully linking these different hardware tools with a unified, integrated software platform...This takes a real systems-level view of design methodology" to allow software and hardware engineers to work more effectively in the design process.
Some background on the EDA market
According to analysts and industry officials, the role of emulation and prototyping processes cannot underestimated in driving forward to commercial reality the most powerful semiconductors used for generative AI and other functions inside data centers at enterprises and the cloud.
Without such EDA (Electronic Design Automation) hardware and software, new chip designs would take years or decades to produce, and the AI revolution and generative AI would not have been possible in the 2020s. Even with widespread use of EDA, it takes two to four years to bring a chip design to commercial readiness. (Emulation is the technique of integrating a new hardware design into a prototyping platform to test it out. Prototyping is then that process of further implementation of a design for testing.)
"EDA is absolutely fundamental to chip design," Balch said. "None of the chips or electronics systems we encounter every day would have come to fruition without EDA software and hardware tools that enable engineers to design, test and manufacture their creations...As AI and other technologies continue to push the boundaries of possibility, the underlying chips must keep rapidly improvement to handle the intense computing requirements we throw at them." EDA tools help engineers "churn out high relliability products on aggressive timelines. Design challenges would be far too great with the automation and algorithmic power that EDA tools provide."
IBM pioneered the EDA field in the 1950s, but EDA approaches have taken on even greater significance in recent years. In addition to Siemens, other major EDA providers include Synopsys, Intel and Cadence. Xilinx, which was purchased by AMD in 2022, still controls 32% of the EDA market, according to 2024 statistics from Metoree, while Synopys and Siemens are tied for second with 20% each and Intel is fourth with 18%.
According to various market surveys, as many as 35,000 US design engineers are directly employed in foundries, but more than 157,000 engineers at US-based OEMs that make cars and a massive variety of electronics that rely on EDA tools. China is estimated to employ another 90,000 chip design engineers.