Researchers reduce design time for DACs, ADCs

digital to analog converter
National University of Singapore's (NUS) Faculty of Engineering has developed Digital-to-Analog (DAC) and Analog-to-Digital Converters (ADC) that can be entirely designed with a fully-automated digital design methodology. (Wikipedia)

The Green IC research group in the Department of Electrical and Computer Engineering at the National University of Singapore's (NUS) Faculty of Engineering has developed Digital-to-Analog (DAC) and Analog-to-Digital Converters (ADC) that can be entirely designed with a fully-automated digital design methodology.

According to the researchers, the design turnaround time for these converters is reduced from months to hours. The reduction in the design effort can benefit cost-sensitive silicon systems, such as sensors for the Internet of Things (IoT). The novel data converter architecture also has low complexity, reducing the silicon area and hence the manufacturing cost by at least 30 times, compared to conventional designs.

The data converters also exhibit the ability to gracefully degrade the signal fidelity when its supply voltage or clock frequency experience wide fluctuations. Such fluctuations are common in energy-harvested IoT sensors, as the power harvested from the surrounding environment is highly erratic. This allows uninterrupted sensor signal monitoring even under unfavorable harvested power conditions, and without voltage regulation.

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The research was conducted in collaboration with Associate Professor Paolo Crovetti from the Politecnico di Torino in Italy, and is supported by the Singapore Ministry of Education and the EU Commission.

"Our research transforms the traditionally analog and mostly-manual design of data converters into fully-automated digital design, reducing the silicon area by an order of magnitude and the design time by two orders of magnitude, allowing semiconductor companies to be cost-competitive while reaching markets faster," said the team leader Associate Professor Massimo Alioto, who is from the Department of Electrical and Computer Engineering at the NUS Faculty of Engineering.

The NUS team demonstrated the concept through several silicon chips implementing both DACs and ADCs with extremely low area. As an example, a 12-bit DAC manufactured in 40-nm standard CMOS technology has been demonstrated with an area equal to the diameter of a strand of human hair. The converter’s ability for technology scaling makes it shrink by approximately another 32 times when implemented in the currently finest technology (7 nm).

The NUS innovation simplifies integrated system design, leveraging the ability to withstand very substantial voltage and frequency fluctuations. The converters also ability to gracefully degrade the signal fidelity when its supply voltage or clock frequency experience wide fluctuations. Such fluctuations are common in energy-harvested IoT sensors, being that the power harvested from the surrounding environment is highly erratic. In turn, this allows uninterrupted sensor signal monitoring even under unfavorable harvested power conditions, and without voltage regulation. Traditional data converters suffer from catastrophic resolution degradation when the supply voltage is below its minimum rated value Vmin (or the frequency exceeds its maximum rated value), hence needing power-hungry circuits for voltage and frequency regulation.

The team is currently working on a paradigm that turns traditionally analog and design-intensive silicon sub-systems into digital standard cell-based designs that are supported by fully-automated design flows, pushing the boundary of classical digitally-assisted design. This research study involves several fundamental sub-systems such as amplifiers, oscillators, voltage and current references, and many others.

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