Packaging technology from Samsung stacks 12 chips

Samsung DRAM
Samsung Electronics has developed the industry's first 12-layer 3D-TSV (through silicon via) technology for DRAM. (Samsung)

Aiming at mass production of high-performance chips, Samsung Electronics has developed the industry's first 12-layer 3D-TSV (through silicon via) technology. The technology  allows up to 12 DRAM chips to be vertically interconnected through a three-dimensional configuration of more than 60,000 through-silicon via holes, each of which is 1/20 the thickness of a single strand of human hair.

According to Samsung, the package’s thickness, 720µm, is the same as current 8-layer High Bandwidth Memory-2 (HBM2) products. This will enable customers to release next-generation, high-capacity products with higher performance capacity, without having to change their system configuration designs. In addition, the 3D packaging technology also shortens data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC)," said Hong-Joo Baek, executive vice president of TSP (Test & System Package) at Samsung Electronics, in a statement.

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"As Moore's law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology."

Samsung expects the new packaging technology to bolster performance of its DRAM chips for high-speed, data-intensive applications. In addition, the company will soon be able to mass produce 24-gigabyte (GB) High Bandwidth Memory, which provides three times the capacity of 8GB high bandwidth memory on the market today.

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