Mentor announces new test products for chip designers

Mentor hopes chip designers can lower costs and work faster with new test tools. (Pixabay)

Mentor announced on Tuesday new design-for-test (DFT) automation technology for chip design teams to reduce costs and speed up chip delivery.

The novel approach of Mentor’s new Tessent Connect product is to let designers work at a higher level of abstraction, rather than relying only on blocks of the entire process. Design teams can collaborate across disparate blocks and use automated tools for set-up, connectivity and pattern generation.

“We are announcing a higher level of abstraction in how the designers interact with these tools,” said Gier Eide, product marketing director of DFT at Mentor, a Siemens business. He spoke in an interview. “Some signals need to accessible at the top level.”

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This higher level of abstraction is a “significant step forward in design tools,” said Laurie Balch, research director for Pedestal Research, in an interview. “You need a broad overview of the overall chip design and not always operate at a lower level of block of design. It sounds like a no-brainer but not something we’ve seen until now. It’s the first time for a tool to come out with that level of advancement with that view at a high level. That is not something others are offering at this point.”

The overall chip test market is dominated by three players, including Mentor, Synopsis and Cadence. Each has specialties where it is more dominant than the other two, Balch said. Overall annual sales are usually just shy of $200 million, a tiny portion of the entire multi-billion-dollar Electronic Design Automation market, which develops software tools for designing integrated circuits.

eSilicon is already using Tessent Connect to meet demanding production schedules for integrated circuits like the neuASIC 7nm for machine learning. Design for test software can be used inside of 2.5 D and 3D chips to test them and debug them. “We are not shipping in volume until our chips are fully operational in customers’ systems, including DFT and IP test,” said Joseph Reynick, director of DFT services at eSilicon, in a statement. “It would be very difficult to meet these challenges without the Tessent DFT portfolio and the efficiencies gained from Tessent Connect Automation.”

Balch said the chip tests typically being done today are run before chips go into production to lower costs but also once the chips are in the field and being used. “Designers want to work out all the kinks before they go into production, but faults can happen any time. You design out the ones you can beforehand, but that doesn’t mean they can’t creep in later on in the lifecycle,” Balch added.

Test software is used by designers in every segment and vertical industry that uses chips, although auto and IoT designs are popular now. “The need for test increases as cost and complexity and size of chips increase,” Balch said.

Several years ago test equipment and the cost of testing became more expensive than the cost of actually manufacturing chips, but test software and design tools have lowered those costs substantially in recent years.

Mentor also announced a Tessent Safety ecosystem to meet IC test needs for autonomous vehicles. 

Mentor called it an open approach to IC based on Built-in Self-test (BIST) software from Mentor. Renesas Electronics is an early adopter of the test technology in its design of a new automotive processor. One in-system logic self-test took one-fifth as long as before, Renesas said in a statement. Mentor Tessent Safety uses Arm Safety Ready IP functions including the Cortex R52 processor.

RELATED: Xilinx ships new Zynq chips for driving vision and control

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