Keysight offering design and test solution for DDR5 memory

Keysight unveils DDR DRAM test solution
Keysight Technologies, Inc. will unveil a design and test workflow solution that reduces product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM). (Keysight)

Keysight Technologies, Inc. will unveil a design and test workflow solution that reduces product development time for Double-Data Rate Dynamic Random-Access Memory (DDR5 DRAM) systems at DesignCon 2020 next week..

DDR5 memory is gaining usage as performance expectations of servers and high-performance computing drive the need for next-generation high-density ultra-fast memory. As the memory runs at twice the data rate of DDR4, it becomes difficult for a hardware designer to optimize the printed circuit board (PCB) to minimize the effects of jitter, reflection and crosstalk. Heavily distorted signals can be recovered with decision feedback equalization (DFE), a new addition for DDR5 DRAM, which disrupts the traditional measurement and simulation approaches used for earlier generations of DDR.

The  design and test workflow solution enables hardware engineers to meet their time-to-market window and deliver a high-performance, reliable end-product with:

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  • New transmitter test methods to measure the signal eye diagram after equalization.
  • New loopback bit-error-rate (BER) receiver tests to validate device and system reliability.
  • Logic analysis to debug complex DDR5 traffic transactions to identify the source of system instability.

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Completing the solution is PathWave ADS Memory Designer for DDR5, a simulation environment that addresses the current challenges faced by designers with the following key features:

  • Ability to predict performance, optimize a design and perform virtual transmitter compliance test, before realizing the first hardware prototype.
  • Reduced simulation setup time from hours to minutes with new features such as DDR components, smart wires and an intelligent memory probe.
  • Increased simulation accuracy for DDR5 by representing receiver equalization with IBIS Algorithmic Modeling Interface (IBIS-AMI) models, enhanced specifically for the requirements of DDR.

“DDR5 is on the horizon, and to secure a competitive edge, organizations are designing their next generation products to take full advantage of it. However, designing for DDR5 will not be the step-and-repeat of earlier generations. The measurements needed to validate memory systems and the simulation technology needed to predict the performance of memory systems are evolving,” said Todd Cutler, vice president and general manager of design and test software at Keysight, in a statement.

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