Intel journeyed through a portfolio of new chip architectures on Thursday in a dizzying set of announcements for upcoming CPUs, GPUs, and IPUs (Infrastructure Processing Units) that the company described as its biggest shifts in a generation.
Intel’s Architecture Day 2021 was held virtually and featured several Intel architects including Raja Koduri who immediately confessed that chip architecture is a kind of “alchemy of hardware and software” that “blends the best transistors for a given engine.”
Intel notably said several of its new chips will be made by TSMC on their top processing node. "Intel has sourced TSMC chips in the past, but this is still a big deal as it is usually is done fairly quietly," noted Jack Gold, an analyst at J. Gold Associates. In the future, the fab capability may come back inside Intel, he added.
Among the highlights on Thursday, two new X86 cores were detailed. There was also a performance hybrid architecture, code-named Alder Lake, for client computing as well as the next-generation Xeon Scalable processor for the data center along with other news. A few highlights derived from Intel’s fact sheet and presentation slides:
-- Performance-core, previously code-named “Golden Cove” is the first of two new X86 CPU cores and is being touted as the” highest performing CPU core Intel has ever built” with a 19% advantage over the current 11th generation Core processor architecture (Cypress Grove) based on several benchmarks.
--The other new X86 core is Efficient-core, previously code-named “Gracemont” for multithreaded performance. It is being called Intel’s “most efficient x86 microarchitecture” and can run a low voltage to reduce overall power consumption. It can also ramp up performance for more demanding workloads. Compared to the Skylake CPU core, Intel’s most prolific CPU, the Efficient-core can achieve 40% more performance at the same power in single-thread performance.
--Alder Lake, a client Soc, is Intel’s first hybrid architecture. It integrates both Performance-core and Efficient-core for duty across all types of workloads. It is built on the Intel 7 process technology and is designed for everything from ultra-portable laptops to commercial desktops It includes improved graphics and low power, among other features. The compute fabric can support up to 1,000 Gbps.
--Thread Director is a workload scheduling technology that will work with Performance and Efficient cores help them work efficiently.
-- A next-generation Xeon Scalable processor, code-named Sapphire Rapids, is for data centers. It includes a tiled, modular SoC architecture that relies on Intel’s EMIB (Embedded Multi-die Interconnect Bridge) packaging technology and will use Intel 7 process technology with the Performance-core architecture. Three data accelerators are built in, including Advanced Matrix Extensions (AMX) for deep learning algorithms to run seven times faster on benchmark tests over Intel AVX-512.
-- Intel’s IPU is a programmable networking device for cloud and communications companies to free up performance for CPUs. Mount Evans is the first ASIC IPU and was developed with a cloud service provider. It integrates design idea from multiple generation of FPGAs.
Intel's architecture news focused heavily on packaging and making SoCs out of chiplets."This is actually a major battleground as complex chips are moving away from monolithic silicon and into packaged subsystems," Gold noted. Intel also announced new GPUs including Ponte Vehcchio, an example of Intel's packaging capability.
"Intel wants to be a supplier of discrete GPUs once again," Gold added, noting that Nvidia and AMD have been capturing the market. "Nvidia and AMD will have some credible competition...GPUs are not only for graphics and gaming anymore."