Intel’s advanced chip packaging prowess took a step forward this week with three pieces of news around boosting bandwidth at lower power and enabling communications among chiplets in a package.
“Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip,” said Babak Sabi, Intel corporate vice president of assembly and test technology development, in a statement.The news broke at SEMICON West in San Francisco.
Chip packaging doesn’t get the respect it deserves in the electronics supply chain, Intel suggested, by noting that it “has always played a critical—if under-recognized—role.” Chip packaging refers to the physical interface between a processor and a motherboard and as such is a landing zone for a chip’s electrical signals and power supply.
Because the electronics industry is entering a data-centric era, advanced packaging “will play a much larger role than it has in the past,” Intel added. “Packaging is becoming a catalyst for product innovation.” Advanced packaging Involves integration of diverse computing engines across multiple process technologies. The goal is to improve performance, lower power and lessen the physical area used in systems.
The first of the three new technologies Intel announced is called Co-EMIB, which is designed to enable more computing performance and capability. Embedded Multi-die Interconnect Bridge (EMIB) refers to a cost-effective method of interconnecting heterogeneous chips, sometimes called 2.5D package integration.
Co-EMIB allows an interconnection of two or more Foveros elements with basically the performance of a single chip, Intel said. Designers will be able to connect analog, memory and other high bandwidth tiles at very low power. (Foveros was introduced by Intel in late 2018 and refers to 3D die stacking in the chip production process.) Intel provided an animation on its website showing the integration of EMIB and Foveros technology.
Intel’s second announcement is called Omni-Directional Interconnect (ODI), a research project to provide greater flexibility for communication among chiplets in a package. The top chip can communicate horizontally with other chiplets (like EMIB) and it can also communicate vertically in the base die below (like Foveros). The ODI approach is designed to raise bandwidth and lower latency through stacking. It also reduces the number of Through Silicon Vias (TSVs) required in the base die, which frees up more area for active transistors.
The third announcement is called MDIO, a new die-to-die interface. It enables a modular approach to system design through a library of chiplet intellectual property blocks. Ultimately, it means better power efficiency and more than doubles the speed and bandwidth offered by Intel’s Advanced Interface Bus (AIB), a PHY level interconnect. AIB was announced by Intel last year as part of a Defense Advanced Research Projects Agency program. In May, Intel released a royalty-free AIB interconnect standard to spur chiplet adoption.
Of all three technologies Intel introduced, Co-EMIB is likely to have the greatest impact. It could be a way to link CPU and GPU cores in the $500 million Aurora supercomputer that Intel and Cray are working on for 2021 delivery, according to EETimes.
The Department of Energy announced Aurora in March, saying it will be the first supercomputer with the performance of one exaFLOP (quintillion floating point computations per second) in the U.S. Its main purpose will be to advance scientific research with high performance computing and AI.
Intel already produces EMIB in Kaby Lake G, an integrated CPU/GPU module. In 2020, Intel plans to ship Lakefield, a laptop processor that uses Foveros.