Intel begins production of Stratix 10 chip with 10M logic elements

Intel's new Stratix 10 is a Field Programmable Gate Array with 10.2 million logic elements for use by designers in the simulation market. (Intel)

Intel has begun production of a new high capacity Field Programmable Gate Array (FPGA) targeted for designers to use in cost-saving chip production emulation systems. 

It is manufactured using an advanced bridging process that logically and electrically stitches together two high-density FPGA dies.

Each die has 5.1 million logic elements, giving the FPGA an extreme density of 10.2 million logic elements to create what Intel claims is the world’s highest capacity FPGA. It has nearly four times the density of its Intel predecessor.

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Multiple customers have already received operational samples of the new Intel Stratix 10 GX FPGA, Intel said in a blog on Nov. 6.

Intended buyers of the new FPGA include the Application Specific Integrated Circuit (ASIC) prototyping and emulation market, including several companies that build commercial off-the-shelf ASIC systems.

Prototyping and emulation systems are used by semiconductor companies to verify complex chip designs prior to production to reduce risk. Such systems can save semiconductor vendors “millions of dollars by helping them identify and eradicate costly hardware and software design bugs before the chips are fabricated,” Intel FPGA Vice President of Marketing Patrick Dorsey said.

“It’s far more costly to fix hardware design bugs after a chip has been manufactured…Because the risk is so high and the potential savings are so large, these prototyping and emulation systems deliver real, tangible value to IC design teams,” Dorsey said.

Because the new FPGA is so dense, it will require fewer of them in an ASIC, System-on-Chip or an application specific product set, Intel said. Some integrated circuit designs may include hundreds of millions of ASIC gates.

Intel competes directly with Xilinx in the large FPGA market, according to Kevin Krewell, an analyst at Tirias Research. The simulation market is relatively small in volume and number of customers, but the chips are high priced. While Intel touted its production ability to build a larger FPGA by connecting two dies, he said Xilinx has been doing the same thing using 2.5 D packaging technology from TSMC.

Intel’s new Stratix “has raised the bar for complexity,” Krewell said. Xilinx announced a Virtex FPGA in August with 8.9 million logic elements.

RELATED: Xilinx to ship gigantic programmable chip with 9M logic cells

Intel’s process of bonding two FPGA dies together into a single package “is a big deal,” added Leonard Lee, an analyst at Next-Curve.  “As we approach the theoretical end to Moore’s Law and scaling, packaging becomes important in improving overall device performance by bringing discrete, similar and dissimilar dies closer together in an efficient and cost-effective package.”

Intel calls its bonding process EMIB, which is short for Embedded Multi-die Interconnect Bridge technology.  The new Stratix FPGA is the first to use the 3D System in Package EMIB to logically and electrically bond two FPGA fabric dies together.  Tens of thousands of connections link the two FPGA fabric dies

“The use of advanced packaging technologies such as EMIB have broader potential to bring about powerful chip designs that integrate heterogenous components into a high-performance device that meets the growing need for domain-specific computing needs that may not be best met by conventional systems,” Lee said in an email. “We are increasingly seeing chipmakers using 3D packaging and chiplet methods to continue to purpose-design and scale their products.”

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