IBM announced Thursday it has created the first chip with 2 nanometer technology.
The company projected it will have 45% higher performance and 75% lower energy use compared to modern 7 nm node chips when put into production.
While 7 nm node chips are widely considered the most advanced for all types of next-generation electronics, TSMC in Taiwan last year began providing 5 nm node production capabilities and is working on a 3 nm node.
IBM first demonstrated 5 nm in 2017 and it took three years for TSMC to bring it to production. By that cadence, the first production of 2 nm chips could emerge in 2024 with use in computers and other electronics afterwards.
IBM said 2 nm chips could quadruple cell phone battery life, speed up laptop functions, and slash the carbon footprint of data centers that would eventually run servers on the smaller chip nodes. One emerging technology that could heavily rely on the new hardware is object detection, with 2 nm allowing faster reactions for robots and autonomous vehicles. A 2 nm channel or other component in a chip is smaller than a strand of DNA.
Anandtech writer Dr. Ian Cutress argued Thursday that a transistor’s density can be a more accurate way to measure a chip’s capabilities. IBM states that its new 2 nm technology can “fit 50 billion transistors onto a chip the size of a fingernail” that is 150 square millimeters, which would put the 2nm transistor density at 333 million transistors per square millimeter.
By that same measure, TSMC’s 5 nm chip has 171 million transistors per millimeter, while its 3 nm chip has 292 million transistors per square millimeter, Cutress noted, using data quoted by the vendor.
Intel often uses density to describe its chips as offering higher density than competitors even at 7 nm and 10 nm nodes, partly to knock down arguments that it has fallen behind in introducing new nodes. Cutress’ data shows that Intel’s 7 nm has much higher density that either TSMC’s or Samsung’s. For example, the Intel 7 nm has an estimated 237 million transistors per square millimeter while the same tabulation is 91 for TSMC and 95 for Samsung, according to Anandtech.
It is significant that IBM described its latest innovation in the new 2 nm chip in the context of a global chip shortage and a protracted effort by chip trade associations and U.S. companies, including Intel, to push for many billions of dollars of U.S. government funding into science research, including for next-generation electronics and chips as well as $50 billion for tax incentives and relief to bring chip manufacturing to the U.S.
“The IBM innovation reflected in this new 2 nm chip is essential to the entire semiconductor and IT industry,” said Dario Gil, SVP and director of IBM Research, in a statement. “It is the product of IBM’s approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D ecosystem approach.”
Engineers and scientists at IBM’s research lab at the Albany Nanotech Complex in New York developed the chip.
IBM does not mass-produce chips as TSMC and other fabs do, but IBM recently announced a partnership with Intel, which is setting up a business unit to do contract work for chip production. Also, Intel is investing $20 billion in two fabs in Arizona and $3.5 billion for a new fab in New Mexico. By comparison, TSMC in Taiwan is planning on investing $100 billion in chip fabs over the next three years even as it builds a new fab in Arizona.
RELATED: Intel invests $3.5B in N. Mexico chip expansion, atop Arizona plans
Gil said in a March blog that the IBM and Intel research collaboration will focus on advancing next-generation logic and packaging technologies, a hint that IBM could with Intel for production of 2 nm chips or a variety of other technologies in years to come.
More transistors on a chip give designers more flexibility to build more powerful processors and energy efficient applications for AI, cloud computing and other technologies. IBM used nanosheet technology in the 2 nm development following that process first introduced in 2017 for 5 nm chips. At that point it had taken IBM 10 years of work by IBM Research. In that process, stacks of silicon nanosheets provide the device structure of the transistor instead of a traditional FinFET architecture. The nanosheet architecture discovery was part of a $3 billion, five-year chip R&D initiative started in 2014 at IBM.
