Chip packaging R&D gets $3B US boost to turn tide

While AI processors and GPUs are sexy and get all the fanfare of late, a big concern is how the US can build up its ability to package chips onto a circuit board loaded inside a server that can eventually render a response to a ChatGPT query.

Advanced packaging of semiconductors is exceedingly complex and involves a series of steps to connect chips to tiny wires that eventually carry data to the outside world. As more chip dies are added to modern boards, sometimes in three dimensions, they are crowded together, take up more space and suck up increasingly greater amounts of electricity while emitting more and more heat.

What’s more, it turns out the US is behind in advanced packaging. As a recent statement from NIST put it, the US is currently “limited in both conventional and advanced packaging capacity. “

More bluntly, Subramanian Iyer, director of the new National Advanced Packaging Manufacturing Program at NIST, said Monday on a conference call with industry officials and reporters, “We do not have advanced packaging in the US capable of high-volume manufacturing.”  He called for the latest  advancements in silicon technology to be applied to packaging, something that NAPMP expects to address.

Last week, Biden administration officials announced $3 billion in funding for the NAPMP, made possible with CHIPS for America funding approved last year. A vision statement was also released.

The $3 billion will be dedicated to an advanced packaging pilot facility (APPF) for validating and transitioning new technologies to US manufacturers. The focus will be across seven areas: materials and substrates; equipment, tools and processes; power delivery and thermal management; photonics and connectors; a chiplet ecosystem; and co-design for test, repair, security, interoperability and reliability.

The first funding opportunity on materials and substrates will be within a few months, Iyer said on the call.

Iyer was especially frank about the status of chiplets used in advanced packaging, as well as co-design. “Everybody gives lip service to the concept of chiplets, but it hasn’t really happened,” he said. “Co-design is another area people give a lot of lip service to.”

The NAPMP will be run by NIST as a government program, while the National Semiconductor Technology Center is a public-private consortium that will work closely with NAPMP under the CHIPS Research and Development Office at NIST.

 The NIST vision document did not set a timeframe for the NAPMP program but NIST officials said on the call that its focus will be on R&D that creates a self-sustaining innovation pipeline the “fuels US packaging leadership” within a decade.

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