Arm and TSMC recently announced a 7nm demonstration chiplet integrated circuit that uses multiple Arm cores and TSMC’s chip-on-wafer-on-substrate (CoWoS) packaging.
The collaboration between the two companies will help designers make high-performance computing system on chip (SoC) systems for cloud-to-edge infrastructure, said Cliff Hou, vice president of technology development for TSMC in a release issued Sept. 26. The first products using the new technology will appear in late 2020, TSMC said at an event in Santa Clara, California.
TSMC, based in Taiwan, is the world’s largest foundry. With Arm and other partners, it is helping lead the semiconductor industry with three-dimensional chips for higher computing power and lower power consumption.
Chiplet designs are intended for modern high-performance computing processors that partition large multi-core system designs into smaller chipsets for greater efficiency. This way, compute functions can be split into smaller separate dies and each chiplet can be made in a different process to achieve lower costs.
TSMC said it has used a custom low voltage interconnect (LIPINCON) to develop the proof of concept. By doing so, TSMC has attained data rates of 8gbps per pin, with greater power efficiency.
TSMC said its chiplet system is made of a dual-chiplet CoWoS using a 7nm process. Each chiplet contains four Arm Cortex-A72 processors and an on-die interconnect mesh bus. It was first produced in April.
A TSMC customer, Cerebras Systems, said it has made a wafer-sized chip with more than 1 trillion transistors and 400,000 computing cores manufactured on a 16nm process, according to EE Times.
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