As the world demands more chips, it is going to take more than new fabs and government grants to produce enough devices fast enough for those who need them. The semiconductor industry also needs faster and more reliable pre-production processes, and that makes emulation and prototyping capabilities an area ripe for time-saving innovations.
AMD’s is aiming the latest entry in its Versal FPGA family at this challenge as it announced this week the Versal Premium VP1902 adaptive system-on-chip, which the company claims is the world’s largest adaptive SoC, with 18.5 million logic cells packed into 77x77 mm of real estate on a four-tile interconnected chiplet, weighing in at twice the density and twice the bandwidth of the previous generation Versal premium device. It also offers eight times faster debugging than earlier products.
Rob Bauer, senior product manager for the Versal line at AMD said FPGA-based emulation and prototyping will offer greater performance and enable faster silicon verification, allowing developers to “shift left,” or move software development and other processes much earlier in the chip design cycle overall and well before silicon tape-out.
“If you think about AI and ML, if you think about autonomous driving or 5G and all of these technologies, all of that relies on super complex semiconductor technology, which frankly takes a lot of time and energy to bring to market, and a ton of work goes into the design and verification of every one of those devices,” Bauer told Fierce Electronics.
“Verification is something that we can directly impact through emulation and prototyping,” he added. “If you could speed up verification, and do more verification, pre-tape-out, you can reduce the risk of bugs and re-spins, etc. Typically, the development team had to wait until they got silicon back to begin software development [which means overall product development and time-to-market takes longer]... Emulation and prototyping allows a software developer to begin software engineering before the silicon is actually available. So we call that ‘shift left,’ or pulling that software development further left in the design cycle, enabling those teams to be productive well ahead of silicon tape-out.”
From a system point of view, there are also benefits, as Bauer pointed out, “It’s all about how many gates can you manage? The highest capacity emulation platform today is around 30 billion gates.” The VP1902, meanwhile, has a 60 billion gates maximum capacity for a single device. And, while AI and other technology trends drive the creation of more multi-chiplet designs with more and more gates, many chip designs needing emulation will fall into a much lower range. While the previous AMD Versal Premium device required 48 devices to manage 1 billion gates for emulation, the VP1902 requires just 24, Bauer said.
AMD worked closely with the top EDA vendors, such as Cadence, Siemens and Synopsys, in designing the VP1902, which is on a fast track to begin sampling next quarter with early access customers, and with productions expected to follow in the first half of 2024.