Workflow Automatically Generates HDL-Verification Test Benches

Microsemi and MathWorks partner to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The integrated FIL workflow with HDL Coder and HDL Verifier from MathWorks lets users automatically generate test benches for hardware description language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, providing rapid prototyping and verification of designs.

 

The collaboration enables users to integrate MATLAB programming environment for algorithm development, data analysis, visualization and numeric computation, and Simulink with Microsemi's SmartFusion2 system-on-chip (SoC) FPGA, and PolarFire FPGA development boards. This allows the stimulation of designs through FIL verification workflow using Microsemi's development boards. FIL verification workflow enables customers to analyze the results back in MATLAB and Simulink.

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Microsemi's SmartFusion2 and PolarFire FPGAs, and their complementary development boards, are available now, and MathWorks' HDL Coder and HDL Verifier are also available now. For more information, visit Microsemi and MathWorks.

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