The Si5381/82/86 multi-channel, jitter-attenuating clocks leverage the company’s DSPLL technology enables the combination of 4G/LTE and Ethernet clocking in a single IC. They eliminate the need for multiple clock devices and voltage-controlled crystal oscillators (VCXOs) in applications such as small cells, distributed antenna systems (DAS), m-BTS, baseband units (BBU), and front haul/backhaul equipment.
As carriers transition to Ethernet-based eCPRI front haul networks to increase the capacity of front haul connections between baseband units and remote radio heads, they are also deploying heterogeneous network (HetNet) equipment at the edge of the network where cost, power and size constraints present unique challenges for hardware designers. Combining 4G/LTE and Ethernet clocking in a single IC dramatically simplifies HetNet clock generation.
The Si538x clocks provide reference timing for HetNet equipment. The Si5386 clock's low-phase-noise DSPLL replaces a discrete clock IC, VCXO and loop filter components in a single-chip design. In addition, the device integrates five MultiSynth fractional clock synthesizers to provide simplified Ethernet and baseband reference timing. This streamlined, single-PLL + MultiSynth architecture provides superior reliability to alternate solutions that rely on multiple PLLs and discrete oscillators.
Like the Si5386 clock, the Si5381/82 devices require no external VCXOs or crystals. All PLL components are integrated on-chip in a 9 mm x 9 mm 64-LGA package. In addition, the Si538x clocks support a hitless switching capability that enables system designers to easily switch between different clock inputs and minimize output clock phase transients, ensuring downstream PLLs remain in lock.
Samples of the Si5381/82/86 wireless clocks are available now, and production quantities are planned to be available in December. Pricing in 10,000-unit quantities starts from $6.77 each for the Si5386 clock. For more details and specs, contact Silicon Labs in Austin, TX at 1-877-444-3032.