SALZBURG, Austria /PRNewswire-FirstCall/ -- EMC-3D is a new consortium created to address the technical and cost issues of creating 3D interconnects using TSV technology for chip stacking and MEMS/sensors packaging. Several major equipment manufactures have joined with material companies to work with key research groups to address the issues of cost-effective manufacturing and integration. Equipment companies initiating the consortium are Alcatel, EV Group, Semitool , and XSiL.
Associate research members include Fraunhofer IZM, Samsung Advanced Institute of Technology, Korea Advanced Institute of Science and Technology, and Texas A&M University. Material members include Rohm and Haas, Honeywell, Enthone, and AZ, with wafer service support from Isonics.
The consortium will develop processes for creating micro vias between 5 and 30 µm on thinned 50 µm 300 mm wafers, using both via-first and via-last techniques. Major processes being integrated into the EMC-3D program are via etch and laser drill, insulator/barrier/seed deposition, micro via patterning with RDL capabilities, high aspect ratio Cµ plating, carrier bonding, sequential wafer thinning, backside insulator/barrier/seed deposition, backside lithography, backside contact metal plating, chip-to-wafer placement and attach, and dicing. In addition, wafer-to-wafer attach, dicing, and debonding will also be demonstrated. The cost of ownership goal for the integrated 3D process is $200 per wafer.
About EMC-3D (or EMC3D)
EMC3D (Semiconductor 3D Equipment and Materials Consortium) was created in September 2006 to develop a new 3D market and technology by demonstrating a cost-effective, manufacturable, stackable TSV interconnection process. TSV processes will be developed for chip integration and MEMS/sensor packaging that are based on plated metal electrodes and thinned wafers. For more information, visit the consortium's Web site.
Contacts for EMC3D members include:
Alcatel, France: Jean-Marc Gruffat, director of business development
Technology: Si and dielectric etching using DRIE
EV Group, Austria: Thorsten Matthias, director of technology, North America
Technology: bonding, thin wafer handling, mask alignment lithography, conformal coat and develop
Semitool Inc, USA: Bioh Kim, director of 3D interconnect
Technology: electroplating, metal/barrier etch, photoresist strip, wafer cleaning and thinning
XSiL Ltd, Ireland: Richard F. Toftness, vice president of business development
Technology: Si laser machining, via drilling, and wafer dicing
Isonics Corp, USA: Kim Bell, director of sales
Technology: wafer service (reclaim and test wafers, wafer thinning, and thick-film SOI wafers)
AZ Electronic Materials, USA: Aldo Orsi, global product manager
Technology: positive and negative acting photoresists
Enthone (Cookson Electronics), USA: Kristian Story, key account and regional line manager
Technology: chemistry for electroplating and metal etch
Honeywell Electronic Materials, USA: Brian Larabee, strategic marketing director
Technology: thermal spreaders, thermal interface materials, and electrical interconnect products
Rohm and Haas, USA: Bob Forman, advanced packaging business manager
Technology: chemistry for lithography, plating, etching, dielectric formation, and bonding
Fraunhofer IZM, Germany: Jurgen Wolf, group and project manager
Korea Advanced Institute of Science and Technology, Korea: Dr. Kyung-Wook Paik, professor
Samsung Advanced Institute of Technology, Korea: Dr. Yoon-Chul Sohn, researcher
Texas A&M University, USA: Dr. Manuel Soriaga, professor