Via significant architectural enhancements, the eleventh generation Tensilica Xtensa processors, Xtensa LX6 and Xtensa 11, allow users to create custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency. Architectural improvements include:
• Enhancements in flexible length instruction extensions (FLIX) for Xtensa LX6 that allow for instructions of any length from 4 to 16 bytes.
• An option for run-time power-down of portions of cache memories, yielding up to 75% local memory power savings in select operating scenarios with dynamic cache-way control.
• More efficient data cache block prefetch lowers system power and boosts system performance by speeding functions such as MemCpy by 6.5 times faster and reducing the total number of system bus read operations by up to 23%.
• Reduced dynamic switching power of the processor logic gates by up to 25%.
For more information, visit http://www.cadence.com/news/xtensa
Cadence Design Systems Inc.
San Jose, CA