Microsemi Announces Family of Frequency Synthesizers and Rate Converters

ALISO VIEJO, CA -- Microsemi Corporation announces the availability of its latest miClockSynth family of high performance frequency synthesizers and rate converters. The new ZL30260-ZL30267 devices, targeted at the enterprise, data center, communications and video markets, simplify board design significantly by generating up to four independent frequency families of ultra-low jitter clock signals from a crystal source or clock input.

Featuring four independent frequency families, best-in-class jitter performance, up to 10 differential or 20 single ended configurable outputs and two fractional-N analog phase locked loops (APLLs) with a fractional and integer divider, Microsemi's miClockSynth devices can create a complete clock tree. The new devices can replace a number of multipliers, synthesizers and oscillators on the board, improving design reliability while reducing bill of materials (BOM) costs and simplifying design. The products also feature an intuitive graphical user interface (GUI) and the ability to create factory pre-programmed devices with ease using Microsemi's web tool, miClockDesigner™.

According to the report from market research firm Databeans titled, "Q4-2015 Timing Devices Market Tracker," the servers and storage area network market will grow to $63 billion in 2016 with an average growth of 11 percent through 2020. Microsemi's ZL30260-ZL30267 devices cater to this growing demand, targeting a wide variety of applications including enterprise switches and routers, PCIe, servers, storage systems, wireless base stations, wireless backhaul, access infrastructure and 1G/2.5G/10G/25G/40G/25G/100G Ethernet.

In addition to the new devices' ultra-low output jitter of 170 femtoseconds (fs) root mean square (RMS), they also offer any-rate frequency conversion—with any input frequency ranging from 10 MHz to 1.2 GHz to any output frequency less than 1 Hz and up to 1 GHz. They feature a highly precise numerically controlled oscillator with steep output frequency per APLL or fractional/integer-N divider with better than 0.01 parts per billion (ppb) resolution. In addition, the devices output format is configurable, with native LVDS, LVPECL, HCSL, 2xCMOS or HSTL per output reducing the number of termination components. The device also features spread-spectrum modulation mode that meets PCIe market requirements.

For more information, visit:


Suggested Articles

Iowa State University researchers are working with NSF grant

Brain Corp. reported a sharp increase in autonomous robot usage in 2Q

Nvidia DGX accelerators helped train system from 150,000 chest X-rays with inference results in less than a second