HSINCHU, Taiwan --- Macronix unveils its new-generation 12 pin-count bus interface. This breakthrough design keeps the high speed, high efficiency features of OctaFlash and uses only 12 pins, sharing the same data I/O, to enable simplicity in system design and optimizes PCB space, resulting in significant cost savings and dramatically enhancing the performance.
Macronix introduced OctaFlash, the world's fastest, high-efficiency 8 I/O Serial NOR Flash with 400MB/s data transfer rate in 2015. The booming development of IoT, the Automotive Electronics markets, the increasing demand for "instant-on" and an "interactive graphical user interface, has driven Macronix to develop and introduce its new low pin-count, high-performance OctaBus memory interface. The new bus interface keeps the low pin count feature of OctaFlash and combines both OctaFlash and the new OctaRAM components on a single bus. The two products can share the same data I/O and certain signal control pins and are designed to be compatible with each other with regards to their modified memory protocols. This enables chipset providers to combine PCB layout designs for OctaFlash and OctaRAM or even use a common PCB design.
In the new OctaBus memory subsystem, OctaFlash is recognized as an industry leader based on its 200MHz high performance frequency; while in tandem, OctaRAM enables designers to optimize their system design with significant cost savings through efficient pin sharing. With its design changed from parallel to serial interface, OctaRAM delivers a performance comparable to DDR2 and allows an improved ease of system design. The embedded systems adopting OctaRAM will, therefore, have a cutting edge advantage. Macronix's new interface is expected to lead the industry evolution to high speed and highly efficient system design in the same way as when Macronix pioneered the NOR Flash transition from parallel to serial interfaces, and become a leader in NVM industry.
OctaBus memory holds more advantages in MCP chip market
With its strengths in low pin count and sharing of the I/O bus, OctaBus memory is expected to achieve great success also in the MCP (multi chip package) market that MCU and core chip vendors are closely watching. The original design of MCP chips, using separate buses, typically requires a BGA package with 80 pins. A design adopting OctaBus can have the package dimension reduced from 9x9mm to 6x8mm. In particular, an MCP combining OctaBus advantages of OctaFlash and OctaRAM in KGD form (known good die), provides even further simplicity of design and reduced complexity to satisfy system manufacturers' critical demands of cost reduction and design flexibility. Macronix sincerely believes that this interface offers such a significant system improvement to designers, and that's the main reason to promote OctaBus memory as an open standard.
Macronix's OctaBus memory subsystem will include three major product lines: Macronix's own OctaFlash series, an OctaMCP product line and a discrete OctaRAM line provided by other memory ecosystem and supply chain partners.
• OctaFlash: 256Mb to 2Gb
• Package: 24BGA (all), 16SOP (256Mb-512Mb)
• Availability: 512Mb in production; rest sampling
• OctaRAM: 32Mb-128Mb 3V/133MHz, 1.8V/200MHz
• Package: 24BGA
• Availability: 64Mb sampling
• OctaMCP: 512Mb (OctaFlash) + 64Mb( OctaRAM), 3V
• Package: 24BGA
• Availability: ES (Engineering Samples) by Jan/2017