SAN FRANCISCO --- Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.
Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure, or by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.
3D-NoC technology has been demonstrated with a homogeneous 3D circuit that is comprised of regular tiles assembled using a 4x4x2 NoC. It also features robust and fault-tolerant asynchronous 3D links, and provides 326 MFlit/s @ 0.66 pJ/bit. It was fabricated in a CMOS 65nm technology using 1,980 TSVs in a Face2Back configuration.
This second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer. The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components.
Moreover, the chip requires 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct-memory-access-type software used for data transmission and has likely industrial uses in virtual-server migration applications.
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