ICs Under The Microscope From ASICs To Custom Devices

ICs Under The Microscope From ASICs To Custom Devices

Sensors Insights by Glenn DeMichele, Guest Contributor

There’s a popular misconception that only large companies can afford a custom ASIC. The first step is to assess if an ASIC could be a reasonable solution in a client’s application. Some requirements might preclude the practical use of an ASIC. For example, the small physical size of an ASIC limits the ability of the ASIC to dissipate large amounts of power. If an initial assessment shows there may be a place for an ASIC in the application the second step requires gathering more details about the ASIC requirements and issuing a formal quotation.


What Is An Integrated Circuit?

An integrated circuit (“IC”) is a small silicon chip upon which a complete electronic circuit is fabricated. Many companies offer general purpose ICs as standard products. These IC chips are commonly supplied in a small package with protruding metal pins. Electronic equipment manufacturers buy and use these ICs as components on a printed circuit board that becomes part of their final product.

Fig.1: A printed circuit board (“PC Board”) containing standard-product integrated circuits.
Fig.1: A printed circuit board (“PC Board”) containing standard-product integrated circuits.


Fig: 2: An IC, circled in red, is cut from the wafer on which it is fabricated, and assembled into a package. The tiny square contact pads on the IC are connected to the pins on the package to ultimately make connections to other components on a PC board.
Fig: 2: An IC, circled in red, is cut from the wafer on which it is fabricated, and assembled into a package. The tiny square contact pads on the IC are connected to the pins on the package to ultimately make connections to other components on a PC board.


Types Of Integrated Circuits

IC is the general term for an integrated circuit. IC’s are also sometimes called “chips”. There are several other names used to further describe the nature of an IC depending on its function or intended market. Regardless of what it is called, the steps required to produce an IC is the same.

Some terms describe an IC based on its intended market.

Standard Product: An IC for general-purpose use and sold to the general public, such as an amplifier or voltage regulator.

ASIC - Application Specific Integrated Circuit: Rather than designing an IC for general-purpose use, ASICs are usually designed especially for one client to provide the specific function required by that client’s end product, hence the term “Application Specific”. For example, a cell phone company may design an ASIC to combine the display backlight controller with the battery charging circuit into a single IC to make the phone smaller and give themselves an edge over their competition.

ASSP - Application Specific Standard Product: Some commercial IC companies also offer devices designed to address a specific application, but offer the device for sale to the general market. For example, a Bluetooth radio IC is specific to one application, but could be used by many different customers.

Other terms are also used to describe an IC based on its electrical function.

Digital IC (or ASIC): The electrical circuits inside a digital IC use logic elements to do digital numerical processing. Examples include microprocessors, Digital Signal processors (DSP’s) and memory chips.

Analog IC: The electrical circuits inside an analog IC use the voltages and currents to perform electronic processing. Amplifiers and voltage regulators are examples of analog IC’s.

Mixed-Signal IC:  A mixed-signal IC contains both analog and digital sections. Mixed-signal IC’s are often some type of sensor which provides real-world data to the microcontroller in a product. A temperature sensor chip for example would use an analog circuit to sense the temperature, then an analog-to-digital converter to change a voltage to a digital number which could be sent to the controlling processor. Another example would be the touch-screen ASIC used in a smartphone.

Reasons To Use ASICs

Size: An ASIC is smaller than multiple interconnected standard products on a PC board. Cell phones are as small as they are because of the presence of ASICs in their design.

Power And Performance: Because of their small physical size, ASIC devices use electrical power more efficiently than a large collection of standard components. In addition, the ASIC contains only the circuitry needed for the application, so an ASIC can often deliver the same or better performance using less power than a design assembled using standard products.

IP Protection: An ASIC protects intellectual property. It is considerably more difficult for an unscrupulous competitor to reverse-engineer and knock-off a product containing an ASIC, as compared to copying a PC board containing standard products.


Competitive Edge

Although an initial investment is required to develop an ASIC, this pays off in the long run. Aside from a possible performance enhancement, a product using an ASIC requires fewer electronic components and is cheaper to assemble. Fewer parts also translate into higher reliability, and the end product’s enclosure might be smaller as well. Using ASICs in a design also reduces the number of component vendors involved in producing the end product, thereby simplifying production planning and purchasing.

NRE And Production Costs Defined


An ASIC must first be specified and designed, and prototype ASICs are then fabricated and tested. This initial effort occurs just once, and must occur before the ASIC can be mass-produced. These costs are called “non-recurring engineering” or NRE costs.



Production wafers containing hundreds or thousands of ASIC chips are periodically ordered. These wafers are then tested, cut up into individual “dice”, and packaged as required. These repeating production costs are incurred whenever more ASICs are needed, and determine the cost of each ASIC


NRE Component Costs

Wikipedia states that “The non-recurring engineering (NRE) cost of an ASIC can run into the millions of dollars.” While this is sometimes true, designs requiring only several thousand dollars of NRE to produce a functional prototype are common. In a typical project, the dominant cost is engineering labor. In this section we will explore in more detail the phases of the ASIC development and discuss what can be done to minimize NRE costs.

Please note: the dollar amounts shown below are estimates based on our experience, and should be interpreted as representative estimates only.

Specification Development  Required

The client starts with a clear idea of how his product will serve the needs of his customer. These customer needs dictate the operational requirements of his or her product, and those product requirements then dictate the specification of the ASIC which will be used in the product. The client’s product is sometimes called the “end application”. This requirement's flow-down concept is best illustrated by a simple example:

  • Customer need: A customer wants a product which will turn off his car headlights automatically after a delay.
  • Client product requirements: Client determines that 30 second delay will accommodate most potential customers.
  • ASIC specification: ASIC shall turn off headlights in 30 seconds ±2 seconds.

The ASIC specification contains many other items as well, such as the operating current, voltage and temperature ranges, device pinout, required packaging, part marking etc. The ASIC specification is essentially a very complete component data sheet.

Before the design of an ASIC can begin, the required function of the ASIC must be well-defined, and the terminal characteristics of the ASIC must be explicitly stated such that “if the ASIC meets the specification, then the ASIC is guaranteed to satisfy the requirements of the client’s end application.”

The specification development phase ends when both the ASIC designer and the client have signed-off on an acceptable specification. One note, the biggest cause of delays is the failure of the client to understand exactly what the ASIC must do to satisfy the requirements of his end-application.

ASIC designers know exactly what to do to make a device that behaves a certain way. What we cannot know however is what the ASIC really needs to do in order to satisfy the client’s product requirements. During the specification development phase, an engineering team must work very closely with the client’s engineering team. Each team will bring design issues to the table that the other team cannot know about. The effort spent during this phase contributes greatly to the value of the ASIC.

Some clients start off with a nearly perfect ASIC specification, which can be signed off in a week. Others take nearly six months to arrive at an acceptable specification. In these longer cases, the client and/or ASIC designer need to do some testing of actual circuitry in the end application to determine exactly what would be required of the ASIC to function properly. In all cases, however, a comprehensive, signed-off ASIC specification is absolutely necessary to ensure that the client’s ASIC performance expectations are met.


Specification Development: $1k $50k

Acceptance Test Plan (“ATP”) Development Required

Hand-in-hand with the Specification, an ATP is necessary to show exactly how prototype ASICs will be tested with hardware to show that they meet the specification. ASIC designers will work with the client to develop and sign off an ATP. If the prototype ASIC devices pass the ATP, the ASIC development is deemed successful and the ASICs will satisfy the client's stated need.

The ATP is also important because during the ASIC design phase, engineers simulate the ASIC design against the ATP to insure the prototypes will pass the ATP. With a good starting Specification, the ATP becomes just a matter of translating the Specification into a set of tests realizable in the simulation environment and on real test equipment.


ATP Development: $1k $10k

Schematic Design Required

With the Specification and ATP in hand, engineers perform the following steps which result in a schematic design of the ASIC. As stated in the last section, the simulation of this design must pass the ATP.

  • Process selection: a semiconductor foundry will fabricate the ASIC. Many different foundries are available, and each of these foundries has multiple fabrication (“fab”) processes available. A particular fab process is selected based on the ASIC requirements such as size, cost, operating voltages and currents, required precision and any other special requirements like tolerance to radiation or high temperature operation.
  • System architecture: alternate methods of executing the function are evaluated, and an architecture review is usually held with the client so we can explain our intended approach.
  • An architecture decision example: implement a multiplier function using analog components rather than using a digital look-up-table. The client review allows us to identify any shortcomings early in the design process.
  • Design of functional blocks: existing IP components, like logic families, amplifiers or voltage references may be used as-is or with some modification. Other special modules must be built “from scratch” using individual transistors, capacitors, resistors, etc. Each functional block is simulated to ensure it performs its intended function.
  • System top-level schematic assembly: the entire ASIC schematic is assembled using the functional blocks.
  • Simulations to ATP: the entire ASIC (where practical) is simulated to ensure it meets every item in the ATP. This simulation is performed over all expected fab process variations (fast and slow NFETs and PFETs, highest and lowest resistor variation, etc.) and over the power supply and temperature ranges specified for the ASIC. If any ATP item fails the simulations, the schematic is altered to make the ASIC pass, and the design is re-simulated in its entirety.
  • Yield estimation: using fab-supplied bounds for lithographic errors, a projection of device yield is made to ensure that the design is manufacturable within the constraints of the program.
  • Design review: a review is held with the client showing how simulations show the ASIC is expected to meet all aspects of the ATP over power supply, temperature and fab process variation.

Due to the wide range of program complexity and ASIC requirements, the scope of the Schematic Design effort can vary dramatically.

There’s also the risk element to consider. The more engineering time spent in design and simulation, the more likely it is that the first prototypes will produce an acceptable ASIC. Engineering time is expensive however, and it may be more cost effective to plan for a second prototype run rather than spend the additional engineering time up front to lower the risk of the first prototype run. On some fab processes, prototype wafer runs can be had for as little as $20k.

On the other hand, prototype runs on more exotic processes, like those with a small feature size or radiation hardened capability, can cost over $200k. In these cases, it is worth the extra engineering effort to run more simulations up-front to further increase the likelihood of first-spin success.


Schematic Design: $5k $250k

ASIC Physical Layout Required

The ASIC schematic is laid out to produce a database of geometric objects on the multiple mask layers used in the selected fab process. This is done at both the lowest transistor-level, and often at higher levels, such as logic gates. After the layout is complete, a Layout Versus Schematic (“LVS”) and fab Design Rule Check (“DRC”) is performed to make sure the schematic was laid out without errors, and that all geometry in the layout conforms to the layout rules specified by the semiconductor foundry. After the physical layout is complete, parasitics are extracted and the design is re-simulated.

A parasitic element is an undesired electrical component in the circuit that is an artifact of the fabrication process and physical layout, and parasitic elements are not included in the original circuit schematic. For example, a wire on the schematic is a zero-resistance connection between two points. In a real ASIC, the wires are made of aluminum, and the resistance of a given wire depends on its composition, thickness, width and length. Since this parasitic resistor was not in the original circuit schematic, the first circuit simulations would not show how this parasitic resistance might affect the circuit operation.

After layout is complete, we extract the value of this parasitic resistance by considering the physical layout of that wire and then modify the original circuit schematic to include this resistance. There are also parasitic capacitances, and even parasitic transistors whose properties depend on the layout. After parasitics have been extracted and included in the circuit schematic, we re-simulate the circuit with parasitics to show that the ASIC still meets the ATP performance criteria.

A layout review is held with the client before submission of the layout to the fab. During this review, the layout is explained, and the ASIC pinout, dimensions and any company logos appearing on the ASIC are verified.


ASIC Physical Layout: $2k $200k

Prototype Tapeout Required

The ASIC layout database is sent to the foundry for fabrication. This is called “tapeout”. Six to twelve weeks later, Sigenics receives typically 3-12 wafers containing the prototype ASIC design. These wafers are cut into die form and assembled into packages to be tested against the ATP. All items in the ATP are evaluated, and any deficiencies or “bugs” are noted. If no bugs are discovered the design moves directly into the production phase.

If bugs are discovered, they may be addressed by a Specification and ATP change, or the design is modified to correct the discrepancy and a second-spin Prototype tapeout is executed. Any required second-spin schematic design and layout effort is usually substantially smaller than what is required for the first-spin. Often, bugs may be corrected by changing only a single mask layer, and the second-spin prototype fab cost and lead time can be significantly less than the first.

Cost for the prototype fab run is dependent on the foundry and fab process chosen. One popular process costs about $20k for 6 wafers. One way to keep the cost of prototypes low is to share a prototype run. Since Sigenics does multiple designs a year, we can often put ASICs from several different clients on the same prototype fabrication run using what is called a “pizza mask”. The cost of that prototype run is then shared between multiple projects, with each client paying for only his fraction of the run. After dicing, all the different ASICs are separated, so confidentiality is preserved.


Prototype Fab: $20k $250k (less if shared)

Purchase of Production Mask Set Required for Large ASIC Volumes

The prototype mask set can be used only once, and can produce 6-12 wafers. If more ASICs are needed, a production mask set must be purchased. This mask set can be used indefinitely to produce wafers in lots of 25. After an acceptable prototype has been fabricated, the same layout database is used to make the production mask set. The cost of this mask set depends on the fab process used.


Production Mask Set: $20k $200k

Production Test Development Required if Testing is Necessary

A probe card is designed, and test equipment is assembled to allow the die on the wafer to be tested on an automatic wafer prober according to a subset of the ATP called the production test plan. A test program is written to implement this production test plan.

The result of wafer probing is a tested wafer and an electronic die map which shows which die on the wafer have passed the test.


Production Test Development: $8k $80k

Production Costs Components

After all of the above NRE tasks are complete, all that remains is to “turn the crank” and produce production ASICs. The primary production cost components are shown in the list below. The three main factors determining the per-die cost of an ASIC are the ASIC die area, the test time and the device packaging. These costs are also volume-dependent.

  • Wafer cost: $800 – $20k per wafer (depends on fab process used)
  • Test time: $0.05 – $3.00 per die (depends on the testing required for each die)
  • Wafer dicing: $400-$2k per wafer (depends on wafer size, #die/wafer and dicing plan)
  • Picking and visual inspection: $0.05-$0.75 per die (depends on level of inspection required)
  • Packaging: $0.15-$5.00 (depends on package type and volume)
  • Shipping and documentation (depends on level of traceability required)


Financial Concerns and Real Examples

Along with the different technical aspects of each ASIC design, the financial environment of every ASIC program is different. On some programs, funding must be spent according to a strict timetable. Sometimes a client may wish to amortize the NRE costs over a production device order. Sigenics is also flexible enough to participate as a financial partner in some ASIC programs.

Shown below are some representative cost examples of ASIC projects.

  • A military-grade analog bus driver/receiver: NRE:$145k, $7.50 in 100k/yr quantities
  • A wireless industrial sensor used to monitor the liquid level in petroleum storage tanks: NRE: $40k, Price/device: $25 in 1k/yr quantities
  • A military-grade IR LED driver: NRE: $60k, Price/device: $1.50 in 50k/yr quantities
  • A multichannel bioelectric amplifier for a research program: NRE: $22k, Price/device: $0 (100 evaluation units supplied from shared prototype run)
  • A radiation-hardened space-grade analog power driver and sensing device: NRE: $850k, Price/device: TBD (pending device yield results)

For more details on ASIC design, visit http://www.sigenics.com/page/ASICs-c


About the author

Glenn DeMichele is the Director of Engineering Sigenics Inc. He received his B.S.E.E. from the University of Illinois, Urbana and an M.S.E.E. from the Illinois Institute of Technology. Prior to co-founding Sigenics, Glenn consulted on satellite and RADAR systems for the Naval Research Laboratory, and was on the engineering staff for Harris Semiconductor, Rockwell/Collins Avionics, Northrop Corp. and Precision Scientific.  He is the holder of 9 patents, and has authored or co-authored numerous papers on neural interface devices. Visit http://www.sigenics.com for more info.