GE Fanuc Announces GHz Digital Receiver PMC/XMC Module

CHARLOTTESVILLE, VA--(BUSINESS WIRE)--Confirming the company's leadership in high performance analog to digital conversion (ADC) solutions, GE Fanuc Intelligent Platforms announced the ICS-8551 rugged ADC PMC/XMC module. Designed for deployment in harsh environments, the ICS-8551 offers both two- and four-channel operation with sampling frequencies of 1.5 GHz (four channel) or 3 GHz (two channel) for software-defined radio (SDR) applications such as spectrum monitoring, signal intelligence, tactical communications and radar.

The combination of high-performance ADC and FPGA resources allows VHF and UHF signals to be digitized and processed directly on the ICS-8551. Algorithms such as digital down conversion, FFT, and filtering can be developed to execute in the onboard Xilinx Virtex-4 FPGA (XC4VFX60 or XC4VFX100), using the included hardware development kit (HDK).

"The ICS-8551 further extends our industry-leading range of Software Defined Radio solutions, pushing back the boundaries of sampling frequency in the XMC format," said Jonathan Jones, Sensor Processing Technology Leader at GE Fanuc Intelligent Platforms. "With its combination of high performance, compact size and available ruggedization, it is ideal for the most demanding ADC applications in both military and commercial environments."

For maximum application throughput, the ICS-8551 provides the user with up to eight lanes of high-speed serial I/O, at rates up to 3.125 GBytes/second, for communication with XMC-equipped carrier cards such as the GE Fanuc Intelligent Platforms V4DSP front end signal processor. The 64/66 PCI interface provides sustained data rates in excess of 400 MBytes/second, while the Pn4 user I/O port allows the user to define direct point-to-point connections to the FPGA, eliminating interrupt latencies. The latter two interfaces may be used for applications in which the XMC interface cannot be used.

The ICS-8551 HDK includes both a default logic core and a Digital Down-Converter (DDC) IP core. The default logic core, designed to provide minimum occupancy of the FPGA, provides a basis for customers to program their own functionality. It includes an A/D interface and data buffering to the high-speed serial outputs and to the PCI bus, via FIFO buffers. The DDC core enables a band-limited signal at a given (programmable) Intermediate frequency to be shifted in frequency to base band, then filtered and decimated prior to output. Output options include the high-speed serial outputs or the PCI bus. Other features including protocol cores will be added to the HDK in future.

Software development kits for the ICS-8551 are available for the VxWorks, Linux and Windows operating systems. Each SDK includes a kernel level driver, full API and application example code written in 'C'. A Flash Loader utility is included to enable users to load FPGA cores to the onboard Flash memory over PCI bus.

About GE Fanuc Intelligent Platforms
GE Fanuc Intelligent Platforms, a joint venture between General Electric (NYSE: GE) and FANUC LTD of Japan, is a high-performance technology company and a global provider of hardware, software, services, expertise and experience in automation and embedded computing, with products employed in virtually every industry, including manufacturing automation, defense, automotive, telecommunications, healthcare and aerospace. GE Fanuc Intelligent Platforms is a worldwide company head-quartered in Charlottesville, VA, and is part of GE Enterprise Solutions.

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