CMOS image sensors (CIS) have experienced very large growth over the last decade with double digit CAGRs in multiple segments and a total market size now over $15B [1]. The largest market driving CIS growth has been mobile which has demanded aggressive pixel scaling to small pixel sizes to deliver increasing resolution within cost and footprint constraints.
For example, the original 2007 Apple iPhone had a 2-megapixel CIS which grew in resolution to 12 Mpixels with a pixel shrink to 1 µm in the 2017 iPhone X. This pixel scaling required the development and adoption of a mass production backside illumination (BSI) technology to illuminate CMOS pixels from the photodiode silicon substrate side instead of conventional frontside illumination from the CMOS interconnect side which blocked increasing percentages of light incident on the pixel with smaller pixels.
The ability to increase sensitivity and improve the chief ray angle illumination optics of micron scale pixels using BSI required flipping and transfer of the CMOS layer to a silicon handle wafer with a very low nm scale distortion to enable backside lithography of the pixel fabrication including the color filter array. Achieving this low distortion requirement was enabled by a direct bond technology capable of sufficiently high bond strength at low temperature such that when a CMOS wafer is simply aligned and placed in contact with a handle wafer, distortion is minimized and not increased with subsequent heating.
The first generation of BSI technology was successfully launched in 2008 with Omnivision [2] winning the camera socket in the iPhone 4 with a 1.75 µm, 5-Mpixel BSI CIS and Sony subsequently winning the iPhone 4S camera socket in 2011 with a 1.4-µm pixel, 8-Mpixel BSI CIS [3]. Samsung launched an ISOCELL variation of the BSI structure in 2013 with deep trench isolation between pixels that controls electron absorption and reduces cross-talk and a Tetra cell version earlier this year that improves low light sensitivity by merging 4 neighboring pixels to work as one bigger pixel in low light conditions.
A second generation BSI technology was launched by Sony in the iPhone 5S in 2013 with a 1.12-µm pixel, 8-Mpixel BSI CIS that partitioned the complex logic and photodiode CMOS system-on-chip (SoC) single wafer process into simpler separate logic and photodiode wafers built in separate process nodes and then stacked with a direct wafer bond and interconnected with a through silicon via (TSV) interconnect resulting in the industry’s first mass produced 3D SoC. This partitioning and stacking enabled significant reduction in process cost and footprint by allowing logic and photodiodes to be fabricated on separate wafers using independently optimized process nodes and foundries. It further enabled the die size to be shrunk from photodiode plus logic areas to primarily the photodiode area.
A hybrid bond improvement in direct bond technology that allowed the elimination of TSVs and associated cost and die area by enabling scalable interconnection between two stacked wafers as part of the direct bond process was initially mass produced by Sony to deliver a third generation 1.4-µm pixel, 12-Mpixel BSI CIS in the 2016 iPhone 6S. A 14-µm hybrid bond interconnect pitch was used outside the pixel array for row/column interconnect and an electrically isolated 6-µm hybrid bond interconnect pitch was used within the pixel array.
Earlier this year, a fourth generation BSI using two iterations of the second-generation direct bond plus TSV interconnect was subsequently used to mass produce a three-layer stack of photodiode, 1-Gb DRAM memory, and logic [4]. The DRAM buffering enabled unpresented performance of 960 fps at 1080p with a 1.4-µm pixel, 12-Mpixel BSI CIS used in the Samsung Galaxy S9. Also this year, Sony announced a fifth generation BSI CIS using a hybrid bond with a per pixel interconnect underneath the pixel array not possible with TSV technology. This enabled a 6.9-µm pixel, 1.5-Mpixels at 660 fps with a dedicated subthreshold ADC per pixel and a global shutter with and -75 dB parasitic light sensitivity [5].
Direct and hybrid bond technology has thus played an enabling role in the realization of BSI and stacked BSI with multiple generational variations of BSI CIS as summarized in Figure 1. The development of these technologies has been led by Xperi for over 15 years [6] resulting in a substantial intellectual property portfolio that has been licensed to CIS industry leaders. The direct bond technology and hybrid bond technologies have been trademarked as ZiBond and DBI, respectively. While BSI CIS has proven to be an excellent early adopter in a wafer-to-wafer (W2W) bond format, there are many other applications and other formats emerging with even greater potential.
A W2W example is CMOS layer transfer to low loss RF substrates for high performance RF front end switches required for applications like 5G. The technology can also be implemented in a die-to-wafer (D2W) format where die are singulated then bonded to a wafer with ZiBond or DBI to realize significant improvement in interconnect density, thermal and electrical parasitics and form factor than possible with conventional bump and underfill technology. D2W applications for the technology include stacked DRAM die for next generation HBM [7], 2.5D die to interposer tiling, and tiled chiplet system-on-chip.
REFERENCES
[1] Yole, “Status of the CMOS Image Sensor Industry”, 2017 report.
[2] Xperi licensee.
[3] Licensee of Xperi Zibond and DBI direct bond technologies.
[4] “Pixel/DRAM/logic 3-layer stacked CMOS image sensor technology”, H. Tsugawa et.al., IEDM 2017.
[5] “A Back-Illuminated Global-Shutter CMOS Image Sensor with Pixel-Parallel 14b Subthreshold ADC”, M. Sakakibara, et.al., ISSCC 2018.
[6] Previously Ziptronix until acquired by Tessera in 2015, subsequently renamed Xperi in 2017.
[7] “Development of Low Temperature Direct Bond Interconnect Technology for Die- to-Wafer and Die-to-Die Applications—Stacking, Yield Improvement, Reliability Assessment”, G. Gao, IWLPC 2018.
About the author
Dr. Enquist is the VP of 3D R&D at Xperi, Inc. He has over 30 years of experience, written for over 130 publications and presentations, and holds over 50 issued US patents related to high speed devices and circuits, low temperature direct bonding, and 3D integration. He holds Ph.D. and M.S. degrees in Electrical Engineering from Cornell University and a B.S. degree in Engineering from Columbia University. He is an IEEE senior member, member of Tau Beta Pi and Eta Kappa Nu.