MOUNTAIN VIEW, CA – CEVA, Inc. unveils The NEW CEVA-X architecture framework, redefining performance and power efficiency for the processing of the control and data planes in baseband applications. Building on the strong heritage of CEVA DSPs in baseband, which have powered more than 6 billion handset processors to date, The NEW CEVA-X addresses the increasing complexity of baseband designs in a wide range of applications and use cases, including LTE-Advanced PHY control, Machine-Type-Communication (MTC) and wireless connectivity.
Featuring a scalable VLIW/SIMD architecture, up to 128-bit SIMD, a variable length pipeline and support for both fixed- and floating-point operations, The NEW CEVA-X delivers 2X more DSP horsepower while consuming 50% less power than the previous generation CEVA-X. The architecture also includes a dedicated 32-bit zero-latency Instruction Set Architecture (ISA), 32-bit hardware division and multiplication, dynamic branch prediction and ultra-fast context switching for the efficient Control processing required in modern baseband designs.
CEVA-X4 - Multi-RAT PHY Control Processor
The CEVA-X4 is the first core based on The NEW CEVA-X architecture, targeting the most complex workloads of multi-RAT multi-carrier PHY control processing in 2G/3G/4G/5G basebands.
The CEVA-X4 was specifically designed to solve the three most critical challenges in next generation modem designs:
• Efficient control processing: for multi-carrier aggregation there is a significant increase in L1 PHY control processing. For example, next-generation Rel-13 LTE Advanced Pro modems are required to deal with up to 5 carrier components in parallel and handle multiple PHY control tasks on multiple carriers, in tandem.
• Powerful DSP processing: a considerable boost in DSP performance is required to support a heavy LTE workload including per-channel measurement, calibration and decoding, as well as legacy RAT.
• Advanced system control: complex system scheduling and data traffic management is essential to deal with the many accelerators, DSPs and coprocessors in the system, within a low latency constraint.
To overcome these challenges, the CEVA-X4 incorporates a unique set of baseband-optimized features and functions in a highly efficient manner. This 128-bit wide VLIW/SIMD processor features 8 MAC units in 4 identical Scalar Processing Units (SPUs) and a 10-stage pipeline, capable of running at 1.5GHz in 16nm and achieves 16 Giga Operations Per Second (GOPS). The processor’s efficient control features include an integer pipeline, a complete 32-bit RISC ISA including hardware division and multiplication, and a Branch Target Buffer (BTB), achieving CoreMark / MHz score of 4.0, 60% better (per thread) compared to the most established in-house DSP used in smartphones today.
For system control, the CEVA-X4 brings a holistic approach to modem design, utilizing the innovative CEVA-Connect™ technology to orchestrate the entire PHY system, comprising of DSPs, coprocessors, accelerators, memories and system interfaces. It is equipped with dedicated hardware coprocessor interfaces and an automated data and control traffic management mechanism that eliminates any software intervention. Its memory subsystem supports an advanced non-blocking 2-way or 4-way caches with hardware and software pre-fetch capabilities.
For more information, visit http://launch.ceva-dsp.com/ceva-x