Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time

SAN JOSE, CA -- Cadence Design Systems, Inc. unveils the Modus Test Solution that enables design engineers to achieve an up to 3X reduction in test time, thereby reducing production test cost and increasing silicon profit margins. This next-generation test solution incorporates patent-pending, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400X without impacting design size or routing.

To address the challenges that come with testing designs, the Cadence® Modus Test Solution includes the following innovative capabilities:

•2D compression: Scan compression logic forms a physically aware two-dimensional grid across the chip floorplan, enabling higher compression ratios with reduced wirelength. At 100X compression ratios, wirelength for 2D compression can be up to 2.6X smaller than current industry scan compression architectures.
•Elastic compression: Registers embedded in the decompression logic enable fault coverage to be maintained at compression ratios beyond 400X by controlling care bits sequentially across multiple scan cycles during automatic test pattern generation (ATPG).
•Embedded memory bus support: A shared test access bus can be inserted to perform at-speed programmable memory built-in self test (PMBIST) across multiple embedded memories in an IP core. New soft programmable test algorithms for FinFET SRAMs and automotive safety applications are also included with this feature.
•Powerful common scripting and debug environment: Design for test (DFT) logic insertion and ATPG capabilities use a new, unified Tcl scripting and debug environment that is shared with the Cadence Genus™ Synthesis Solution, the Innovus™ Implementation System and the Tempus™ Timing Signoff Solution.

For more information on the Modus Test Solution, please visit http://www.cadence.com/news/modus
 

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