ams releases interoperable PDK for its 0.35µm analog specialty processes

Premstaetten, Austria --- ams AG announces the availability of its first interoperable process design kit (iPDK) for its 0.35µm analog specialty processes. iPDKs are based on the OpenAccess database and use standard languages as well a unified architecture to enable interoperability among multiple EDA vendor tools.

The new iPDK v4.10 significantly improves the time-to-market for highly competitive products in the analog intensive mixed signal arena. This comprehensive design environment with its highly accurate simulation models and parametrized device layouts (PyCells) based on the programming language Python provides a proven route to silicon.

ams’ new iPDK v4.10 supports the high performance 0.35µm process technologies C35 (CMOS), S35 (SiGe-BiCMOS), and H35 (High-Voltage CMOS). The ams iPDK comes complete with silicon-qualified digital, analog and RF library elements, complete sets of low voltage devices (3.3V and 5.0V) and high-voltage devices (10V, 20V, 50V and 120V devices) with various gate oxide thicknesses. Area-optimized high-density digital libraries, both for 3.3V and 5V as well as a wide selection of digital & analog IO libraries are available for the entire 0.35µm process family. Fully characterized simulation models for a large set of simulators, extraction and verification run sets for both, Calibre and Assura and automatic layout device generators (PyCells) are included. Hence product developers are enabled with a plug-and-play tool set which facilitates "first time right" designs with EDA vendor tools of their choice.

The new iPDK is based on ams’ industry-leading and benchmark design environment (hitkit) and is available for its specialty processes C35, H35 and S35. The iPDK has been tested & qualified with Keysight EEsof EDA Advanced Design System (ADS) 2016.01 and Synopsys Galaxy Custom Designer 2014.12.

For more info, go to http://asic.ams.com/iPDK410
 

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