SAN JOSE, CA -- Altera Corporation acceopts the Global FPGA Technology Innovation Leadership Award from analyst firm Frost & Sullivan. The award highlights Altera's implementation of IEEE 754 single-precision hardened floating point DSP (digital signal processing) blocks in its Arria® 10 FPGAs--enabling a processing rate of up to 1.5 TFLOPS (Tera floating point operations per second) offering greater energy efficiency and productivity in digital system design. Altera's programmable devices enable customers to optimize their designs in big data and search applications, data center acceleration, military communications and high performance computing, which need more precise calculations. Download the award summary report at http://bit.ly/1jSACuI.
Frost & Sullivan research analyst and collaborator on the report Viswam Sathiyanarayanan stated, "While many semiconductor companies have attempted to implement floating point operators into FPGAs, they reported to Frost & Sullivan they have not been successful in delivering efficient performance, reducing power consumption, and increasing speed at the same time. Some of the competing DSP systems and GPUs (graphic processing units) provide support for floating point calculation, but Altera's Generation 10 FPGAs deliver this capability along with the ubiquitous connectivity and hardware flexibility available with FPGAs."
The Global FPGA Technology Innovation Leadership Award is awarded under the Frost & Sullivan Best Practices Awards Program, which recognizes best-in-class products, companies and individuals.
"We are honored to be recognized for our technology leadership in delivering the first FPGAs and SoCs with hardened floating point operators," said Alex Grbic, senior director of software, IP and DSP marketing at Altera. "With this innovation, Altera FPGAs and SoCs offer a performance and power efficiency advantage over microprocessors and GPUs in an expanded range of applications."
The research also calls out Altera's industry-leading Quartus® II software tools, the Altera SDK for Open CL™, and Stratix® 10 FPGA with its HyperFlex™ architecture.